If there are number of files in EDA playground (SV/UVM), including the the packages, etc., how does EDA playground take care of compile order? Is the package file compiled first?
If it doesn't care about compile order, what should be done to take care of that?
When you select the SystemVerilog option on EDA Playground, two files are compiled: testbench.sv and design.sv. If you want any other files compiled, then you need to use `include. For example, in https://www.edaplayground.com/x/296, you'll see that my_testbench_pkg.svh is included at the top of testbench.sv
`include "my_testbench_pkg.svh"
and my_sequence.svh and my_driver.svh are included at the top of my_testbench_pkg.svh:
`include "my_sequence.svh"
`include "my_driver.svh"
This is inconsistent with VHDL on EDA Playground, where all tabs are automatically compiled. However, I cannot think of an easy way to change this, because if I made it so that all tabs were compiled with SystemVerilog it would not be backwards-compatible with older playgrounds that used `include.
