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I created a fifo memory in vhdl but i have some problems with it. To be more exactly i put 16(capacity of memory) elements in my memory but when i want to read from memory i can just read 14 elements.(My empty signal becomes 1 too early). Here is the code: code

Alexandru Prodan
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    It is customary to put the code IN the question. – Oldfart May 08 '18 at 17:06
  • A mention that i forget:I simulated in active-hdl so i did't use clock divider or debouncer – Alexandru Prodan May 08 '18 at 17:12
  • Your question doesn't provide a [mcve]. –  May 08 '18 at 18:03
  • I put code that i wrote (i know it's not minimal but it's pretty hard to put just a piece of code because i used components and people should now how i connected them - maybe there is the problem) and i said what my problem is by describing it (i give an example in question).Sorry i forget something..Can you help me ? – Alexandru Prodan May 08 '18 at 18:21
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    Converting some of the variables in the process in STATUS to signals seems worthwhile for waveform troubleshooting. Their equations look like they originated in a CPLD design (and none of the grouping parentheses are needed). This `a := q(0) and not q(2) and not q(3) and not q(3);` looks erroneous, probably should be `a := q(0) and not q(1) and not q(2) and not q(3);`. That get's all 16 values out of the FIFO. outdata could also be shifted with a one clock host holdover for issuing pop from EMPTY false by enabling dataout reg all the time in RAM. Provide a [mcve]. –  May 09 '18 at 02:37
  • A MCVE doesn't have to be big and elaborate, the problem exists wholly in fifo_status.vhd which generates status flags and operates a counter (c4ud.vhd) specifying the number of items in the FIFO along with the full and empty flip flops (whose outputs aren't signals). You'd only need a testbench that generated ce_wr, ce_rd and clk. Converting variables in the process to signals assigned in concurrent assignment would allow everything to be visible in a waveform display (the problem was actually noted by proof reading). –  May 10 '18 at 01:45

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