VHDL multiplexing and two outputs

Question

I need your help. I have a VHDL with nested condition and I would like to redraw it into a schematic. I think I should use one 2bit mux and 4bit mux. Is there anyone who can help me please? I tried google it but I didn't find anything that can help me.

process (a,b,c,d) begin
    y <= '0';
    z <= b;
    if d='1' then
        y <= b;
        if a = '0' then
            y <= c;
        end if;
        z <= '1';
    else
        y <= '1';
        z <= d;
    end if;
end process;

a,b,c,d are std_logic in

z, y are std_logic out

Welcome to StackOverflow. Could you clarify your actual question? I don't know what you mean with "redraw into a schematic". Do you want to make a drawing? — JHBonarius, May 01 '18 at 11:25
I will give You a tip : look at the output signals, `z` depends only on signal `d` state, and the `y` depends on two signals (`d`,`a`)states. And additionally as You can see signals `d` and `a` are the controlling signals. So `z` will be output from 2bit mux and `y` will be output from 4bit mux, and `d` will be switching 2bit(2:1) mux and `a` and `d` will switch 4bit(4:1) mux. — Take_Care_, May 01 '18 at 12:04

score 1 · Answer 1 · answered Jan 20 '22 at 12:41

This a code for a 4-bit mux you can easily modify to make 2 bit

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

 ENTITY mux_4_1 IS
PORT (
    a : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
    b : OUT STD_LOGIC);
  END ENTITY;

   ARCHITECTURE behavioural OF mux_4_1 IS
   BEGIN
PROCESS (a, s)
BEGIN

    IF s = "00" THEN
        b <= a(0);
    ELSIF s = "01" THEN
        b <= a(1);
    ELSIF s = "10" THEN
        b <= a(2);
    ELSE
        b <= a(3);
    END IF;
END PROCESS;
END ARCHITECTURE;

VHDL multiplexing and two outputs

1 Answers1