32-bit Divider in Verilog with Finite State Machine Control

Question

I am trying to implement a 32-bit divider in Verilog and I am having issues. A and B are the numbers to be divided. Here is my code so far. The output of the testbench is:

What am I doing wrong? Also, what does it mean when the output is both Hi and Low at the same time? This is being implemented in EDAPlayground:

Design and Testbench

You dont seem to be asserting `start` in your waveform so its unclear what the problem might be — Unn, Apr 26 '18 at 22:33

score 1 · Answer 1 · answered Apr 26 '18 at 22:57

Unsure if this is your only problem, but you are casing on nextstate in your combinational logic block in the control path. You should be casing on state (ie, it should not be case (nextstate) but case (state))

You should also not be setting load, run, err and ok in both the always @(posedge clk or negedge reset) register block and the always @(*) combinational block in the control path, they should only be assigned from the combinational block.

32-bit Divider in Verilog with Finite State Machine Control

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