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I'm new to coding verilog.

This is code for a 3-bit Comparator. I need help adding a signal called 'US' (unsigned/signed) to my testbench code. When the signal is High(unsigned mode), the Comparator interprets the numbers as Unsigned numbers. When the signal is Low (Signed Mode), the Comparator interprets the numbers as signed numbers. 

module comparator(A,B,G,E,L,US);
  input [2:0]A;
  input [2:0]B;
  input US;
  output G,E,L;

  reg G,E,L;

  always@(*)
  begin
    if(US==0)
      begin

        L=$signed(A)<$signed(B);
        E=$signed(A)==$signed(B);
        G=$signed(A)>$signed(B);
      end
    else 
        L = A < B;
        E = A==B;
        G = A > B;
    end  
endmodule

TEST BENCH CODE:

`timescale 1ns /1ps
module comparator_tb();
  reg [2:0]A=3'b000;
  reg [2:0]B=3'b000;
  reg US;
  wire G,E,L;
  integer i,j;

  comparator uut(A,B,G,E,L,US);

  initial begin 

    for(i=0;i<8;i=i+1) 
      begin 
        for(j=0;j<8;j=j+1)
          begin
           #50
           B=B+1;
           end
        A = A+1;
        B=3'b000;   
      end
  #100
  $stop;
  end
endmodule
JHBonarius
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redbulln
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  • You already **have** a signal `US` which switches between signed and unsigned. So why are your asking *how to add an input...?* – Oldfart Apr 20 '18 at 18:12

1 Answers1

0

i guess you want to toggle US in your test bench. something like the following?

since US is declared as wire (default), you need the assign statement:

integer us_count;
assign US = us_count;

initial begin 
 for(us_count = 0; us_count < 1; us_count++) begin
  for(i=0;i<8;i=i+1) 
  begin 
    for(j=0;j<8;j=j+1)
      begin
       #50
       B=B+1;
       end
    A = A+1;
    B=3'b000;   
  end
 end
 #100
 $stop;
end

if you declare it as reg, you can use it directly in the loop instead of the us_count and do not need the assign

reg US;
initial begin 
  for (US = 0; US < 1; US++)
  ...

The rest depends on how you want to test it.

Serge
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