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Is it possible to use assign keyword with module instances?

Lets assume I have a module logarithm which works as it's intended. In some other module, I want to have: A = log(B) + log(C).

Is there any efficient way other than the following to do so?

wire [3:0] logB;
wire [3:0] logC;

Logarithm log(logB, B);
Logarithm log(logC, C);

assign A = logB + logC;

And is it known as a gate-level design or a data-flow one? If it is not data-flow, would you please present a data-flow alternative to this code?

Reza Abdolhakim
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  • you need to start reading about verilog basics. it is very different from regular programming languages. – Serge Apr 20 '18 at 16:00

1 Answers1

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Well your assign keyword in the code is not working on module instances. Rather, it is working on the outputs of those module instances.

The way you are assigning to A should help you get the desired output provided you have set its width accordingly. And it is a data flow representation

There is one mistake in your given lines of code though. You can not use the same instance name log for both the instantiations of the module Logarithm. They have to be unique.

kevin1494
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