getting FFGEN from Verilog Synthesizer

Question

Whenever I pass the following behavioral code through Design Vision synthesizer, I get the FFGEN instances, meaning the synthesizer is treating my logic as having latch, even though it's supposed to be completely combinational.

Code:

module decoder(input  [1:0] Op,
input  [5:0] Funct,

output reg[9:0] controls);

    // Main Decoder
 always @(*)  begin
    case(Op)
    // Data-processing immediate
    2'b00: if (Funct[5]) controls = 10'b0000101001;
    // Data-processing register
    else controls = 10'b0000001001;
    // LDR
    2'b01: if (Funct[0]) controls = 10'b0001111000;
    // STR
    else controls = 10'b1001110100;
    // B
    2'b10: controls = 10'b0110100010;
    endcase
 end
endmodule

Could anyone advise how to modify the code so that I can use my own design library for the output structural verilog

Also a search with the keywords 'Verilog' and 'Latch' gives 121 hits most of which are applicable to your situation. — Oldfart, Apr 13 '18 at 05:11
Possible duplicate of [What is inferred latch and how it is created when it is missing else statement in if condition.can anybody explain briefly?](https://stackoverflow.com/questions/22459413/what-is-inferred-latch-and-how-it-is-created-when-it-is-missing-else-statement-i) — Greg, Apr 14 '18 at 15:25
Hello.. thank you everyone should much for replying. Yes specifying all the cases did the trick of removing latch logic. But I still get Flup flop logic. I do no understand how that makes sense. Can't this logic be represented purely combinationally ??? — LearningCurve, Apr 15 '18 at 19:29

score 0 · Accepted Answer · answered Apr 13 '18 at 08:03

0

This is a very common mistake to make. Your case items do not cater for all the possible values of the case statement expression Op.

You can fix it by adding a default statement towards the end, after your last case item.

For further reading, there is an excellent answer by Greg here - What is inferred latch and how it is created when it is missing else statement in if condition.can anybody explain briefly?

answered Apr 13 '18 at 08:03

kevin1494

158
2
10

@LearningCurve you should not be seeing any sequential logic generated for this. I am not sure why you are seeing it but you can share your updated code for us to take a look – kevin1494 Apr 16 '18 at 05:32

Sumit Panse · Answer 2 · 2019-03-05T11:00:27.047

-2

Just keep in mind of all the dependencies and enlist them inside the sensitive list. Also, as mentioned by toolic, don't forget to add the default case in your case statement as the last case for it.

edited Mar 05 '19 at 11:00

answered Apr 13 '18 at 11:01

Sumit Panse

9
4

I know that (*) is appropriate but still, keeping the sensitive list makes it simpler to avoid FFGEN error. – Sumit Panse Apr 14 '18 at 17:46

getting FFGEN from Verilog Synthesizer

2 Answers2