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For example, LDR r0,[r1, #4]!, r1 value will be changed to r1+4 then load value to r0, however, when I tried to use LDR r0,[r1, r2]!, r1 didn't changed.

I'm working with TM4C123GH6PGE and CCS 5.4

HMD
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mjet
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2 Answers2

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According to the architecture reference manual write back is not supported when using a register as offset.

Johan
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6

Use a better assembler that doesn't silently distort your code when you try to assemble something that's not encodeable. Or if it did print a warning message, don't ignore warnings!

.syntax unified
.thumb
LDR r0,[r1, #4]!
LDR r0,[r1, r2]!
LDR r0,[r1, r2]

assembled with arm-none-eabi-as -mthumb -mcpu=cortex-m4 arm.S: GAS says arm.S:4: Error: Thumb does not support register indexing with writeback -- 'ldr r0,[r1,r2]!' instead of assembling it into ldr r0,[r1, r2] or something.

(Cortex-M4 supports the entire Thumb2 instruction set, and gas knows this. I don't think there's a way to directly enable Thumb2 with any option with a name that includes thumb2, only with -mthumb or .thumb and a -mcpu=CPU or -march that supports Thumb2.)

It assembles fine in ARM mode, where LDR r0,[r1, r2]! is encodeable:

   0:   e5b10004        ldr     r0, [r1, #4]!
   4:   e7b10002        ldr     r0, [r1, r2]!
   8:   e7910002        ldr     r0, [r1, r2]
Peter Cordes
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  • @old_timer: Good call, I should have said in the answer that I already did try with `-mcpu=cortex-m3`, which supports the full Thumb2 instruction set, in case there was a Thumb2 encoding for this. (There isn't.) Updated. Tried with cortex-m4 as well just in case, because Wiki says there are some Thumb2 insns that m3 doesn't support. But I think that's just saturating instructions, not addressing modes. – Peter Cordes Apr 12 '18 at 11:59
  • m3 was the first one with thumb2 out and it is armv7m based, the m0 which came later is armv6m based, armv6m if you count them up added a dozen or two thumb2 extensions to the classic thumb instruction set. the armv7m added over 100 new instructions. so on top of everything else we have in our minds three thumb instruction sets (adding to the prior ones not replacing). But you can catch arm in rare cases with version numbers and they are using version numbers bigger than three. then the unified syntax just leads people into this trap asked by the op instructions from one set... – old_timer Apr 12 '18 at 13:07
  • not supported by another. using -mthumb by itself with a stock build of binutils gives armv4t level instructions, so to get any thumb2 at all on assembly you need to specify a cortex-m or the right cortex-a or the architecture. then to get the right level of thumb2 even more detail. just painful. I prefer to use old fashioned original thumb when i can as it is supported across the board from the arm7tdmi to the present although the armv8 has to be in armv7 compatibility mode. then use thumb2 for that target if I need performance. – old_timer Apr 12 '18 at 13:09
  • the m4 and m7 refer to armv7m so I honestly have not looked to see if those added instructions over the m3, would not expect that would have expected a new architecture. the m23/m33 if I am remembering right and/or the new revs of docs have made it worse, as of the armv7m it would say "all thumb variants" and then for thumb2 specify armv6m and armv7m or armv7m alone. a manual I saw not long ago simply put the current architecture on all instructions with little help to figure out the all thumb variants or other cores, not that it was that manuals job to do that.... – old_timer Apr 12 '18 at 13:14
  • @old_timer: My wikipedia link has a table. It says M3 is missing some saturating instructions, while M4 has them. – Peter Cordes Apr 12 '18 at 13:17
  • thanks Ill have to check that. the m4 certainly added floating point, a very reduced percentage of the full sized set, single precision and not sure if reduced within that. the m7 has float as well have to look to see if they added double. of course that is chip vendors option to compile these things in even if they are not marked as optional in the TRM. – old_timer Apr 12 '18 at 13:29
  • arm burns a ton of "CPUID" registers which at times go deep into individual or groups of instructions supported by the core you are using. do not have the visibility to know if the chip vendors can cherry pick those or if that is a generic solution to cover different architecture families... – old_timer Apr 12 '18 at 13:30
  • @old_timer: That table shows all of those things, including M4 having optional single-precision float, while some later Cortex CPUs have optional single/double precision float, and so on. – Peter Cordes Apr 12 '18 at 13:31
  • my comments were in reference to what the wikipedia page refers to as thumb-2 instructions which the m3,4,7 support the entire set. but it reall is a mess...up to the m23 which I dont have one yet (does anyone?) where good old thumb1 is supported, I try to stay within the thumb1 as best I can. – old_timer Apr 12 '18 at 13:33
  • yep, the trm should also indicate that floating point is optional, near the beginning of the trm it has a section if any optional items are available like halfword vs word size fetching, systick, float, etc. but the chip vendor gets the sources so they can hack away at it, at their own risk. like caching on the m4,ST has their own flash caching scheme so the dont support caching on the m4 (one/ones I have tried, if I have my experiments straight) which I dont think is listed in the optional section of the trm, but is of course trivial to defeat (of nothing else stub out the sram interface). – old_timer Apr 12 '18 at 13:37
  • good table/reference BTW, thanks I usually open up all the manuals and try to sort it out... – old_timer Apr 12 '18 at 13:44
  • @old_timer: I usually don't get into enough detail on ARM to care about what any specific CPU actually has, just ARM in general. I normally do x86, where backwards / forwards compatibility is the major reason for the continued existence of the entire ISA :P (and there aren't that many different models, so it's not as hard to track which features were new in what). – Peter Cordes Apr 12 '18 at 13:51
  • hmm, dont agree with some of the text in there (wikipedia), but better than nothing...with x86 you still have the problem of can I use the new instructions or not, not as severe as the arm world as most of the x86 platforms being used daily by average users have most of what you are after, older machines without some instructions are not generally on the radar as the OS is old and not supported by new code, etc...8051 had this issue long before arm, not so much the instruction set but the special function registers. – old_timer Apr 12 '18 at 13:57
  • @old_timer: yup, x86 gets new instructions regularly, but you can reliably detect support for them at runtime using well-defined `cpuid` feature-detection. Or you can check tables to see what has what. They come in large batches of named features, like BMI2, or AVX512BW. (AVX512 is starting to enter ARM-like mix-and-match territory, though, where Xeon Phi (Knight's Landing) has some AVX512 extensions, Skylake-server has others, and there's a common subset... https://en.wikipedia.org/wiki/AVX-512#CPUs_with_AVX-512 for a table.) – Peter Cordes Apr 12 '18 at 14:07