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I am looking to transfer data from the zynq ddr to a custom ip, then store the result on the sd card. The sd card is connected through the emio pin, so it is available to the PL. So far, I can access the DDR from Windows, so I put files there. All I need is to connect each component in vhdl to send and receive data from each other. My current Block diagram has AXI stream FIFo, AXI DMA, BRAM generator, and BRAM controller. I've read different tutorials, and only find how to set up the hardware, but not how to connect each piece. Any ideas? Block Design

EE_minor
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    "All I need". Then try something. We're not going do your work for you. We can however help you with debugging your code. – JHBonarius Apr 06 '18 at 08:00
  • I am not asking you to solve this for me. I'm asking if anyone can point me in the right direction. – EE_minor Apr 06 '18 at 16:12
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    [UG895](https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug895-vivado-system-level-design-entry.pdf)System-Level Design Entry, System-Level Design, Entry Chapter 3 Working with Source Files, Creating and Adding Design Sources. (If this doesn't appear helpful it may be because you're question is unclear due to lacking specifics ("Any ideas?"). –  Apr 07 '18 at 00:35
  • Thank you – user1155120. I'll be more specific. Right now I have implemented a mass storage device through software (sdk) that creates a disk drive on the host computer, and stores whatever data is placed in into the sd card on the zybo board. My question now is, how can I take this data, now stored on the sd, and pass it to a peripherial (maybe ddr) so that I can now have access to this data through the pl (programmable logic) side of the fpga? Since the sd0 is connected to MIO pins, I don't have access to the data through hardware which is where my vhdl code is to do stuff with the data – EE_minor Apr 16 '18 at 19:17

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The easiest way is using a Linux distro to access the SD card.

Afterwards you can use AXI4 or AXI4S to communicate.

DMA is you friend to copy data from RAM to AXIS and back.

If you want to transfer data directly using AXI4 you can test it with devmem from busybox by accessing the corresponding register. This can be AXI BRAM Controller or AXI GPIO for example.

akira hinoshiro
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