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VHDL and Verilog serve the same purpose, but most engineers favor one of both languages. I want to find out who favors which language.

There are dozens of myths and common wisdoms about the separation between Verilog and VHDL. (ASIC / FPGA, Europe / USA, Commercial / Defense, etc.) If you ask around, people will tell you the same thing over and over, but I want to find out if these myths are based on reality.

So my question: can anybody provide sources of quantitative data that indicate who uses VHDL and who uses Verilog? Again, I’m looking for numbers, not for gut feelings and general indications.

Philippe
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  • Good luck. Even the market survey of the US that Cooley quoted was based on $$$$ (money spent on simulators at the time Verilog simulators were more expensive) rather than users. – Jim Lewis Nov 05 '13 at 16:56
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    Voting to close as off topic, since this is a market share question, or too broad. Related: http://electronics.stackexchange.com/questions/16767/vhdl-or-verilog || http://electronics.stackexchange.com/questions/26547/do-you-use-vhdl-nowadays – Ciro Santilli OurBigBook.com Oct 05 '15 at 08:40

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VHDL and Verilog are both fairly new and fairly specialized languages. Those two characteristics make their qualitative data hard to come by. On the other hand, we can use these characteristics to our advantage. We can attempt to infer the popularity of these languages based on the number of references that are available.

Amazon.com Book Listings By Subject

VHDL        315
Verilog     132

Google Trends: Verilog (red) vs VHDL (blue) - SourceVerilog(red) vs VHDL(blue)

By these numbers (and only these numbers) VHDL seems to be more widely-used than Verilog; however, there is no indication on the market share details of each.

Fitz
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    Thanks @Fitz. This tells us that VHDL is bigger than Verilog. Or at least, people use Google more to search for VHDL answers than for Verilog. Still, I was hoping for more demographic data (east coast vs west coast, military vs commercial etc.) Google trends does help a lot, but for smaller search volumes, it refuses to give any data. For example, Google Trends only gives you very limited information for VHDL/Verilog searches in different states of the US. – Philippe Feb 14 '11 at 09:55
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    "fairly new and failry specialized"? Specialized yes, but not new. VHDL and Verilog are only new if you consider Perl to be a new language. They were all created in the 80s. They've both evolved and were enhanced over the years, but they aren't new. – Ross Rogers Feb 15 '11 at 17:18
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    This could just mean that VHDL is less well documented, and needs to be searched more? What is interesting is the downtrend on that graph. There is no way vhdl and verilog use is declining, so concluding one is more used than the other is...not right. But it is an interesting data point. – SDGator Jul 04 '12 at 16:51
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I've been an ASIC and FPGA designer/verification engineer for 17 years, and I've worked on both VHDL and verilog projects. I've been at some huge name companies that use VHDL (Intel, Qualcomm, Lockheed, Raytheon). However, all the IP I've ever seen is in verilog, for whatever that's worth. Also, from my limited sample of job interviews and experience, its been pretty evenly divided between VHDL and Verilog over most of my career.

My take on it is that VHDL and Verilog were pretty even until the mid-2000's, when Verilog evolved into System Verilog, and VHDL stayed fairly static, except for minor changes. It used to be that VHDL had more non-synthesizable language features that aided verification that old-school verilog. With System Verilog, VHDL got leap-frogged in that area of strength, and never responded with an evolution of its own, so I'm (anecdotally) seeing a migration towards SV and away from VHDL.

SDGator
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    With OSVVM, VHDL has leap-frogged SystemVerilog by adding functional coverage, constrained random, and built-in Intelligent Testbench capability - and it is free. See http://osvvm.org and http://www.synthworks.com/blog/osvvm – Jim Lewis Nov 05 '13 at 17:02
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    Interesting. I'm not sure if it can really be that powerful without being object-oriented, though. I can get a fantastic amount of reuse and flexibility from OO that I'm not sure would be possible otherwise. I'm willing to look into it, though. Are any of the major simulators supporting this? – SDGator Nov 05 '13 at 22:10
  • What verification needs is data structures. OO is just a clever way to create some of that. WRT functional coverage and more specifically cross coverage, SystemVerilog is heavily restricted by its declarative approach. With SV you are only ok if the cross coverage is a simple Cartesian product. If you need something other than a Cartesian product you are stuck with an awkward masking process. If you need different coverage goals for your bins, then with SV you are out of luck. OSVVM also supports built-in Intelligent Testbenches - Only possible with SV with a expensive tool. – Jim Lewis Dec 15 '13 at 19:57
  • Lets be honest about the reuse in SystemVerilog. Most of the reuse in SV is about creating the infrastructure. In VHDL our "reuse" approach in this case amounts to using existing language constructs for creating structural code - and by using the same language constructs that RTL engineers do for creating structure we don't alienate them like is done in SV. – Jim Lewis Dec 15 '13 at 20:00
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At Texas Instruments, Verilog was more popular. My experience is that designers can use whichever they prefer, usually, and most agree that Verilog is easier to use and the code is shorter (fact) than equivalent VHDL. Just check any text book that has both, and you can see that difference in length of code.

Clint Halsted
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    Agree that Verilog is shorter. But I don't see any evidence that "most agree that Verilog is easier." – Philippe Apr 12 '13 at 06:35
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    If you're looking at a textbook that has examples coded in both, it is probably not using VHDL very effectively. –  Nov 06 '13 at 09:20
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I work for a large publicly traded hardware design company headquartered in Silicon Valley. We used to use VHDL, but switched to verilog in 2002(ish).

Around 2008, we switched to system verilog. As I understand it, most non-military/non-gov't contracting companies use system verilog while military/gov't contracting entities use VHDL these days.. but don't quote me...

Is this what you're asking for? If so, +1 for system verilog :)

DaveD
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    Hi @Dave, I was hoping for more hard numbers, like x% on the West Coast uses Verilog. Defence is y% VHDL. z% of VHDL designers use VHDL. I wanted to find out this stuff because over all, VHDL seems (a bit) more popular than Verilog (see @Fitz' answer) but when I talk to people, many say that they are using Verilog. – Philippe Mar 14 '11 at 14:15
  • Seems like you're looking for an industry analyst... sorry, I don't know these numbers or where to find them :(. However, one cannot conclude anything w.r.t. overall HDL usage percentages from the graph below.. it could be saying that learning VHDL requires more support, or could mean that VHDL is more popular in academia. – DaveD Mar 14 '11 at 22:41
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I don't have the numbers nor any gut feelings for that matter. I'll give you some facts regarding VHDL.

[1] SystemVerilog enhances Verilog-HDL up to par with existing capabilities of VHDL (STD. 1076-2002).

[2] VHDL 2008 (STD. 1076-2008): Has anyone used the latest standard. Kindly use it and then compare with Verilog (STD. 1364-2005).

[3] SystemVerilog extends Verilog-HDL by adding a rich, user-defined type system, and adds strong-typing capabilities, especially in the area of user-defined types. ... HOWEVER the strength of type-checking in VHDL still exceeds that in SystemVerilog. ... The downside of Strong-typing is on performance; i.e. Compilation and Simulation (only when run-time checks are enabled) are slow. Slow compilation is not an issue when considering the amount of investment in the project (the reasoning at our firm).

I consider VHDL as a 'safe' language and Verilog as a 'fast' language that lets you write models quickly. The company where I work prefers safety over speed; so we use VHDL predominantly in our design flows.

Also do check out the new OS-VVM (Open Source VHDL Verification Methodology) developments.

Renjith
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