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I'm currently working on an FPGA design using SDaccel (and Vivado HLS). My design have several sub-components, and the latency (clock cycles) of each sub-component would depend on the input data at runtime (Therefore Vivado HLS analysis window would not be able to give me exact latency values). How do i measure the timing of each component in my design, so i can figure out where my bottlenecks are?

I found a pragma directive (pragma SDS trace), but i'm not sure how to use it to give me a detailed view of what is happening in the system during execution of different inputs.

Are there pragmas in Vivado_HLS that allow this? If so, How do i use them?

Thanks W

OLUWOLE JAIYEOBA
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2 Answers2

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The SDS pragma seems to apply only if you're using SDSoC, which supports Zynq and Zynq MPSOC.

If you're just using Vivado HLS, it looks like you need to incorporate tracing and measurement code in a more manual fashion.

In simulation, you could use the waveform view to see when each subcomponent receives data and produces output.

I often add trace or counter logic in my RTL for this purpose, so that I can measure latency and throughput on the FPGA as well.

A common pattern I have is to have an event FIFO to which I enqueue timestamp, event type, and event value. To make it non-blocking, only enqueue if there is room in the FIFO.

Jamey Hicks
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In addition to the methods explained in Jamey's answer, the Vivado HLS user guide describes a TRIPCOUNT pragma that specifies the number of iterations a loop should take.

Also, when using C/RTL cosimulation, the report should contain measured latency and throughput numbers, based on the input samples that were used during the simulation.

haggai_e
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