How to get FLOPS in RISC-V using SW or HW method?

Question

I am a newbie to RISC-V. I wonder how I could get FLOPS using SW or HW method. I try to use CSR to get FLOPS, but there are some problems.

As I know, if I redesign the hpmcounter which counts every floating operation event, I could get FLOPS by using the csr read instruction. I know there is a similar design in the rocket-chip-based SiFive's U54-core manual. In the manual I can see SiFive core has sophisticated feature counting capabilities. This feature is controlled by the mhpmevent CSR. If I set lower eight bits of mhpmevent as 0, and enable the [19-25] bit, I can get counter value from mhpmcounter. I actually want to design this field like SiFive core.

I try to imitate it for FLOPS, but I encounter some problems.

1. I can't access to the mhpmcounter, and I can see the illegal instruction error like following link. illegal instruction error message!!

I make a simple test code and compile it successfully, but there is a illegal instruction error when I implement it using spike and cycle accurate emulator. Both use proxy kernel.

  // simple test code

  unsigned long instret1 = 0;
  unsigned long instret2 = 0;

  float a,b,c;
  a = 5.0;
  b = 4.0;
  asm volatile ("csrrs %0, mhpmcounter3, x0 " : "=r"(instret1)); 
  c = a + b;
  asm volatile ("csrrs %0, mhpmcounter3, x0 " : "=r"(instret2));
  printf("instruction count : %ul \n", instret2-instret1);

2. It is hard to change to M-mode from user mode for access to the mhpmevet and mhpmcounter. In the RISC-V priv-spec 1.10, I find xRET instruction can change mode. Following text is about xRET in the spec.

The MRET, SRET, or URET instructions are used to return from traps in M-mode, S-mode, or U-mode respectively. When executing an xRET instruction, supposing xPP holds the value y, x IE is set to x PIE; the privilege mode is changed to y; x PIE is set to 1; and xPP is set to U (or M if user-mode is not supported).

If someone knows it, I hope to see the detailed assembly code.

3. I try to modify rocket-chip/src/main/scala/rocket/CSR.scala for redesign CSR. Is it the only way? Firstly, I want to use spike to test the counter value. How should I change the code?

If anybody has some other ideas or has accomplished it, please point to me. Thanks!