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I am writing verilog code (behavioural) for a 16-bit ALU. I am facing compilation error:

module alu_16bit(out,a,b,op);

output reg [15:0] out;
input [15:0] a,b;
input [2:0] op;
reg [15:0] e ;
reg [15:0] d ;

parameter op_add    = 3'b000 ;
parameter op_sub    = 3'b001 ;
parameter op_sl     = 3'b010 ; // shift left
parameter op_sr     = 3'b011 ; // shift right
parameter op_sar    = 3'b100 ; // shift arithmetic right
parameter op_nand   = 3'b101 ;
parameter op_or     = 3'b110 ; 

always @(*)
begin
case(op)
op_add  : out <= a+b ; 
op_sub  : out <= a-b ; 
op_nand : out <= ~(a&b) ;
op_or   : out <= a|b ; 
op_sr   : out <= a >> b ;
op_sl   : out <= a << b ; 
op_sar  : begin
            if(b>16'd15)
                out <= {16{a[15]}} ;
            else
                out <= {b{a[15]},a[15:b]} ;
          end

default: out <= 4'bzzzz ; 
endcase
end

endmodule

I am facing compilation error in this line of op_sar:

out <= {b{a[15]},a[15:b]} ;

This is the error I am receiving:

alu_16bit.v:65: error: Syntax error between internal '}' and closing '}' of repeat concatenation.
Mohit Garg
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1 Answers1

1

This line

out <= {b{a[15]},a[15:b]} ;

is no good for two reasons:

i) I think you meant

out <= {{b{a[15]}},a[15:b]};

and

ii) both {b{a[15]}} and [15:b] are illegal because b is not a constant.

So, as you seem to want sign-extension and so want signed arithmetic, why not make out signed and use the >>> (arithmetic shift right) operator, which will handle the sign-extension for you?

Matthew Taylor
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  • Thanks a lot! Can you also provide a link to a reference that contains this? I am referring a book and it doesn't contain this >>> operator. I also searched online, many websites didn't have it! – Mohit Garg Mar 28 '18 at 16:31
  • @MohitGarg The arithmetic shift operators and signed types were introduced in 2001. This is not new stuff. They are described in the 1800-2012 standard, which is free to download. Verilog no longer exists as a separate standard - it is merely an unofficial subset of SystemVerilog. – Matthew Taylor Mar 29 '18 at 08:12