Currently I am trying to follow the MathWorks tutorial 1 to register a TE0720 with a TE0701-6 carrier board in Matlab. I followed the instructions, designed the block design and exported it as advised. Using the Matlab HDL Workflow Advisor I can follow unitl step 4.1 Create Project. Here, I get the following error message:
invalid command name "CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK"
while executing
"CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} CONFIG.PCW_IOPLL_CTRL_FBDIV {30} CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} CONFIG.PCW_IRQ_F2P_INTR {1} CONFIG..."
(procedure "create_root_design" line 49)
invoked from within
"create_root_design """
(file "vivado_custom_block_design.tcl" line 986)
while executing
"source vivado_custom_block_design.tcl"
(file "vivado_create_prj.tcl" line 15)
This is regarding the exported block design in the corresponding *.tlc file.
After deleting the line mentioned in the error, the error persists, but for the following line. This holds true until I deleted all lines following
CONFIG.PCW_IMPORT_BOARD_PRESET {preset}
It seems to me that once the preset for the board is imported, all following commands are seen as invalid. If I put this line in the end of the list though, I get the error
ERROR [Common 17-69] Command failed: Missing name/value pair in -dict argument.
If I remove this line, I get the error
ERROR [BD 41-1811] The interconnect </axi_interconnect_0> is missing a valid master interface connection
ERROR [Common 17-39] 'validate_bd_design' failed due to earlier errors.
Is there a way to fix this or what is the problem here?
EDIT: I am using Vivado 2017.4 from the Vivado HL WebPACK. Could it be that there is a feature not available in this version for rebuilding the project as MATLAB intends to do?
EDIT 2: I started the complete tutorial fresh from scratch again and now I only get the error
ERROR: [BD 41-1811] The interconnect </axi_interconnect_0> is missing a valid master Interface connection
when going throught the HDL Workflow Advisor. As far as I understand the issue, Vivado searches for something to connect the axi_interconnect to. But isn't this the interface port (DUT) as described later in the tutorial (end of step 2 in Register the custom reference design in HDL Workflow Advisor, where the compiled simulink model should be connected?
