IAR Linker placing of packed structures

Question

I'm struggling with the IAR linker using packed structures.

This is a structure to be placed at an absolute position:

typedef __packed struct
{
    uint8_t au8Build[8];
    uint16_t u16Type;
} stMetaInfo_t;

#pragma location = ".META_INFO"
const __packed stMetaInfo_t c_stMetaInfo =
{
    .au8Build = { 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U },
    .u16Type = 0x0059U
};

The size of the structure is 10 bytes and I verified it using sizeof().

Linker configuration:

place at address mem: 0x08003FE0 { readonly section .META_INFO };

I'd expect the linker to put exactly 10 bytes of data at the location but I can see a size of 12 bytes (0xC) in the map file:

"A1":                                             0xc
  .META_INFO              const    0x08003fe0     0xc  myfile.o [1]
                                 - 0x08003fec     0xc

... and the toolchain creates an additional hex file that shows the 2 bytes that are being added by the linker:

0x08003FD0 = ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
0x08003FE0 = 00 00 00 00 00 01 02 03 59 00 !00!00! ff ff ff ff 
0x08003FF0 = ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff

I assume that the linker is using the classic 4-byte alignment since it's a 32-bit CPU but how can I force the linker to place only 10 bytes? Later on, the structure should be moved at the end of a specific memory region. So I don't want to have any padding bytes.

I'm using IAR Embedded Workbench for ARM Version 8.22.

Best regards Jay

score 0 · Answer 1 · answered Mar 26 '18 at 11:54

The extra bytes are introduced by the compiler not the linker. In the compiler, static memory has an alignment of 4-byte, which implies that each data section is padded up to a multiple of 4 bytes. This behavior can not be changed by command line switches or pragmas. The only way around it is to define the meta info structure in assembler instead of C.

IAR Linker placing of packed structures

1 Answers1