Verilog, How to pass different parameters when I use generate to instantiation module?

Question

I have a question about parameters passing. I used generate for to do module instantiation. But how to pass different parameters to each module? For example:

generate
   for (i=0;i<N;i=i+1) begin:ModIns
       Mod #(.p1(?),.p2(?)) M (
       // Signal connection
       );
   end
endgenerate

For N modules, each with different p1 and p2. How to do that? By the way, the number of parameters is very large, can I pass parameters as a file? Thanks!

score 1 · Answer 1 · answered Sep 29 '21 at 04:35

Here are my 2 cents. Declare a 2-D register and store all the parameters there.

reg [31:0] param_mem1 [N-1:0]; //Assuming parameter size to be 32 bit wide
reg [31:0] param_mem2 [N-1:0];

always@(posedge clk)
begin
 for(i=0;i<N;i=i+1)
 begin
   param_mem1[i] <= i; //Here replace 'i' with your actual parameter value
   param_mem2[i] <= i+1; //Dummy assignment, please use intended values
 end
end

generate
 for (i=0;i<N;i=i+1) begin:ModIns
   Mod #(.p1(param_mem1[i]),.p2(param_mem2[i])) M (
   // Signal connection
   );
end
endgenerate

score 0 · Answer 2 · answered Mar 04 '18 at 10:23

0

First: No you can't read it from a file. Parameters have to be known at compile time and a file is only readable in run time.

You can derive them from a genvar or pass them through a hierarchy, but then it more or less stops. Maybe what you are trying to do can be solved in a different way but the scope of the problem you have outlined for us here is rater limited.

As always: Tell us your problem, not your solution.

answered Mar 04 '18 at 10:23

Oldfart

6,104
2
13
15

Actually, I need to build many hundreds even thousands of modules only with different parameters like length, width, weight, etc. I don't want to put them as input because there are gonna be too many. Is there a better way? – Mar 05 '18 at 06:52
No, what you are talking about sounds like a library. You could make a Perl or C program to generate the source code. That is what is normally used to generate libraries. – Oldfart Mar 05 '18 at 07:02

score 0 · Answer 3 · answered Mar 04 '18 at 15:30

It would be easier to do this in SystemVerilog because a parameter can be an array, and your generate loop could select an element for each iteration of the loop. In Verilog, you can pack your elements into a bit-vector, and your generate loop could select a slice for each iteration of the loop.

parameter A1={8'd1, 8'd2, 8'd3, 8'd4, ...};
parameter A2={8'd9, 8'd8, 8'd7, 8'd6, ...};
generate
   for (i=0;i<N;i=i+1) begin:ModIns
       Mod #(.p1(A1[i*8+:8),.p2(A2[i*8+:8])) M (
       // Signal connection
       );
   end
endgenerate

If you want to define the parameters from a file, you can put the parameter declarations in a separate file and `include the file.

In the Verilog, I can't do bit select to parameter. If I pack them into a bit vector, Do I need to treat them as inputs? — , Mar 05 '18 at 06:42

score 0 · Answer 4 · edited Sep 29 '21 at 05:58

0

This compiles with VCS:

genvar port_idx;
generate
for (port_idx = 0; port_idx < 5; port_idx++) begin : intf
    xactor_t xactor (core_clk, core_rst);
    defparam xactor.intf_id = 18 + port_idx;
end

edited Sep 29 '21 at 05:58

m4n0

29,823
27
76
89

answered Sep 29 '21 at 03:53

Dustin

11
2

Verilog, How to pass different parameters when I use generate to instantiation module?

4 Answers4