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While implementing a state machine on VHDL I was wondering how can I set the output / current state initial condition. I read on one of the questions on here.

One of the answers said we do the initialization before the case structure: 

process(currentstate, a)
begin
  b <= '1';
  c <= '1';
  case currentstate is
    when s1 =>
      if (a = '1') then
        c <= '0';
      end if;

      nextstate <= s2;

However doesn't that make us automatically set b<='1' and c<='1' whenever we get into the process? So if we are at a state say A and we are at the conditions of moving to B whenever we enter the process this directly puts b<='1' and c<='1' isn't that true ?

Or does it actually just run once we start the program and then gets bounded in the case structure ?

Also check this link.

In their FSM implementation they did not specify the initial state how does the compiler or FPGA determine the start state ?

scary_jeff
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TheDataScientist101
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1 Answers1

3

The lines you are looking at are not performing initialization.

b <= '1';
c <= '1';

Remember that VHDL is a hardware description language, not a programming language. What those two assignments do is to set a default assignment for those signals, unless something else contradicts these assignments later in the process. You can assign to the same signal several times in one process, and whichever assignment happens last will take priority. This saves having to write code like:

case State is
  when s1 =>
    a <= '0';
    b <= '1';
    c <= '1';
  when s2 =>
    a <= '1';
    b <= '0';
    c <= '1';
  when s2 =>
    a <= '1';
    b <= '1';
    c <= '0';
end case;

It can end up being quite repetitive and error prone to have the same assignments in many states, so default assignments can really tidy it up:

a <= '1';
b <= '1';
c <= '1';
case State is
  when s1 =>
    a <= '0';
  when s2 =>
    b <= '0';
  when s2 =>
    c <= '0';
end case;

The same pattern works for if statements where you don't want to cover every output signal in every logical branch.

If you want an initial state, there are two approaches that may be applicable depending on the scenario. Here you would assert reset at start-up to set the initial state. Note that the case statement is inside a clocked process:

process (clk)
begin
  if (rising_edge(clk)) then
    if (reset = '1') then
      State <= s1;
    else
      case State is
        when s1 =>
          State <= s2;
        when s2 =>
          State <= s1;
      end case;
    end if;
  end if;
end process;

The other option is to define your state signal with an initial value:

signal State : state_type := s1;

I won't go into the pros and cons of using initial values as there are existing questions that explore this.

scary_jeff
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  • In the code I supplied through the link how does the FPGA interpret the initial condition if the programmer didn't state it explicitly ? – TheDataScientist101 Mar 01 '18 at 15:11
  • They have implemented a reset in their clocked process, as per my example. They have implemented a two-process state machine, which is pointless, you can put everything into one clocked process, as per my example. – scary_jeff Mar 01 '18 at 15:13
  • Okay so when downloaded to FPGA they have to start the system by resetting it first ? – TheDataScientist101 Mar 01 '18 at 15:16
  • Yes, you would have to assert and release the reset signal to put the state machine into the initial state. – scary_jeff Mar 01 '18 at 15:17
  • Okay one last thing if the code was downloaded to the FPGA and no reset button was pressed how would the system behave? – TheDataScientist101 Mar 01 '18 at 15:18
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    Strictly speaking, the behavior would be undefined. In an SRAM-based FPGA, the default initial value will be zero, which would normally correspond to the first state in your enumerated state type (`Zero` in the example you linked to). If you specify a different encoding for the state machine in the synthesis tool (for example one-hot), I'm not sure what would happen. – scary_jeff Mar 01 '18 at 15:24
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    For a numerated type, the default value will always be the first value. i.e. `type state_type is (s1, s2);` then `signal state : state_type` will default at `s1`. – JHBonarius Mar 01 '18 at 21:38
  • @scary_jeff In VHDL, objects are always initialized to there leftmost value independent of a provided encoding scheme by attributes or constraint files for synthesis. FPGAs support initial values that are not `0`. In Xilinx FPGAs, both logical values can be programmed as an initial and reset value. In Intel FPGAs, the non-zero initial value is emulated by inverting the D-FF output value. – Paebbels Mar 03 '18 at 15:00