VHDL-“Signal cannot be synthesized, bad synchronous description”

Question

I have a error while Synthesize this code in Xillinx. This error is: "Signal Z_1 cannot be synthesized, bad synchronous description"

entity uk3 is
     port(
         rst : in BIT;
         C : in INTEGER;
         clk : in BIT;
         S : out INTEGER
         );
end uk3;

--}} End of automatically maintained section

architecture uk3 of uk3 is
begin
    process (C,clk,rst)
    variable Z_1 : integer:=0;
    begin
        if rst='1' then Z_1:=0;
        elsif rst='0'and clk'event and clk='1'and C=1
            then 
            Z_1:=Z_1 + 1;
        elsif rst='0'and clk'event and clk='1'and C=2
            then
            Z_1:=Z_1 + 2;   
        else
            Z_1:=Z_1;
        end if;
        S<=Z_1;
        end process;

     -- enter your statements here --

end uk3;

why? Pls

Don't ask the same question twice. – JHBonarius Jan 18 '18 at 12:29 — JHBonarius, Jan 18 '18 at 12:29

Staszek · Answer 1 · 2018-01-18T12:51:14.673

1

You probably should properly describe your synchronous process. This is not c/c++, you should use proper template for that, or it will not synthesize. I particular, you should only have one statement sensitive for edge of the clock.

For example:

process (clk,rst)
variable Z_1 : integer:=0;
begin
    if rst='1' then 
        Z_1:=0;
    elsif rising_edge(clk) then
        case C is
            when 1 =>
                Z_1:=Z_1 + 1;
            when 2 => 
                Z_1:=Z_1 + 2;
            when others =>
                null;
        end case;
        S<=Z_1;
    end if;

end process;

Note, that there is no C in sensitivity list, as it is not needed. If there is no rising edge, it will not fire anyway (it is synchronous to rising edge of the clock)

I havn't tested this code, but it should work.

And actually, why don't you make Z_1 signal, instead of variable?

edited Jan 18 '18 at 12:51

answered Jan 18 '18 at 08:30

Staszek

849
11
28

Teraz nie da się wykompliować: architecture uk3 of uk3 is begin process (clk,rst) variable Z_1 : INTEGER:=0; begin if rst='1' then Z_1:=0; elsif rising_edge(clk) then case C is when 1=> Z_1:=Z_1 +1; when 2=> Z_1:=Z_1 + 2; end case; D<=Z_1; end if; end process; -- enter your statements here -- end uk3; wyskakują errory Podczas kompilowania: . – Pietryno Jan 18 '18 at 08:59
# Error: COMP96_0093: uk3.vhd : (47, 21): Actual parameter types in subprogram call do not match subprogram formal parameter types. # Error: COMP96_0301: uk3.vhd : (48, 4): The choice OTHERS must be present when all alternatives are not covered – Pietryno Jan 18 '18 at 09:00
@Pietryno See also [my answer here](https://stackoverflow.com/questions/36539962/errorxst827-signal-count-cannot-be-synthesized-bad-synchronous-description/36543625#36543625). – Matthew Taylor Jan 18 '18 at 09:20
@Pietryno Your comments seem to be another question. If so, please ask another question. – Matthew Taylor Jan 18 '18 at 09:21
1

i would suggest using synchronous reset. And to make `Z_1` a signal instead of a variable. – JHBonarius Jan 18 '18 at 12:27
I agree with JHBonarius. And you actually get your answer in compiler message:) You need to comver all cases in case statement. Edited. Also don't use polish language here, this way only me and few other people will be able to understand you. – Staszek Jan 18 '18 at 12:53

VHDL-“Signal cannot be synthesized, bad synchronous description”

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