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I am doing some simple tests to evaluate how clock speed increases in a digital circuit when pipelining.

I pipeline an 10to1 mux using 2 5to1 and 1 2to1. I get some clock speed increase from the fpga synthesizer (altera). Then I add one more stage, replacing the he 5to1 muxes with 2to1 and 3to1 and appropriate registers. In the latter case the clock speed drops. I don't get why adding registers and pipeline stages would drop the clock speed..any explanations?

Hdllrn
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  • Fpga does not have muxes. The synthesis tool translates and optimizes your VHDL code to logic that fits in the FPGA building blocks. Routing delay between the blocks is often dominating. – JHBonarius Dec 30 '17 at 17:00

1 Answers1

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The minimal logic gate in most FPGAs is a lookup table (LUT) They came with 3 to 6 inputs. Altera's ALMs are configurable in many ways. In either way, if a multiplexer size is lower then the equivalent LUT size, there will be no further Fmax improvement.

You could describe all multiplexer sizes as trees of 2:1 multiplexers. Synthesis will optimize the resulting equations and map them to LUT structures and configurations of your FPGA device.

You can further use a user-defined rising_edge function to create a variable pipelining:

function registered(signal Clock : std_logic; constant IsRegistered : boolean) return boolean is
begin
  if IsRegistered then
    return rising_edge(Clock);
  end if
  return TRUE;
end function;

(Source: PoC-Library - components package)

This function allows you to selectivly enable and disable pipeline stages.

Paebbels
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  • do you mean that if the minimum LUT input number is 3 , it is not recommended to 'break' a 4to1 mux in two 2to1 ? – user2609910 Dec 31 '17 at 15:26
  • E.g. Xilinx has LUT6 structures. This matches a 4:1 mux with 4 data inputs and 2 select signals. Any smaller mux will result in a LUT6 structure with unused capabilities. – Paebbels Jan 01 '18 at 01:11