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How to count the number of flip-flops generated or used in the Verilog code without using any tool?

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Cœur
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Vineet dubey
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  • What did you tried ? – Al Foиce ѫ Dec 24 '17 at 08:33
  • for a small piece of code, the number of times the clock edge is getting triggered, I am calculating the change in variables which can give me a rough count of the number of flops that might be getting used while running the code. but if we have a large number of variables which is changing simultaneously then how to check the number of flops in the code? – Vineet dubey Dec 24 '17 at 10:11
  • It's impossible to help you since you have not provided any code of what you're trying to do. SO is not a code writing service, so you need to provide code and links to the relevant sources you are using, yourself. – not2qubit Dec 24 '17 at 13:31
  • Sorry sir, code is very big, I will be not able to provide you code – Vineet dubey Dec 24 '17 at 15:26
  • It is very difficult to calculate the number of flops manually, in particular in the big models. There are generate blocks which you need evaluate manually. there are optimizations which could alter number of flops. There are complicated always blocks where is difficult to figure out the outcome. So, all your attempts will be just a rough estimation in the best case. – Serge Dec 24 '17 at 21:14
  • I have attached snippet of my code. Can you use it as a reference to explain to me how to proceed to count the number of FFs used – Vineet dubey Dec 25 '17 at 10:06

1 Answers1

0

You count the number of bits on the LHS of non-blocking assignments inside an always @ (pos/neg_edge ...). (The 'non-blocking' adjective is superfluous as you should only have non-blocking assignments inside an @ (pos/neg_edge clock) section.)

The following code produces 12 registers:

reg [7:0] my_byte1,my_byte2;
...
always @(posedge clock)
begin
   my_byte1     <= something_which_is_8_bits_wide;
   my_byte2[3:0]<= something_else_which_is_4_bits_wide;
end
Oldfart
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