Verilog If statement - Signal is not a Constant

Question

I am just trying to execute a simple If - Else statement in Verilog but somehow it does not work

module my_mod(A,B,C);
input [3:0] A; 
input [3:0] B; 
output [4:0] C;

if(A>B)
assign C=A;
else
assign C=B;

endmodule;

Below is the error message:

 "xvlog -m64 --relax -prj adder_tb_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "F:/Verilogcodes/Sources/my_adder.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module my_mod
ERROR: [VRFC 10-60] A is not a constant [F:/Verilogcodes/Sources/my_adder.v:6]
ERROR: [VRFC 10-1040] module my_mod ignored due to previous errors [F:/Verilogcodes/Sources/my_adder.v:1]
WARNING: [VRFC 10-2502] extra semicolon in $unit (global) scope [F:/Verilogcodes/Sources/my_adder.v:11]

I am sure it is related to the post - "<signal> is not a constant" error in if-statement. But I feel difficult to spot out the exact logic on why assign statements within If statements won't work. Any assistance/suggestion on why the above code is not working will be helpful.

score 1 · Accepted Answer · answered Nov 26 '17 at 15:21

An if/case/for statement outside of a procedural context is a generate construct. See section 27 of the 1800-2012 LRM. These constructs must have constant expressions because they will be optimized away at compile time.

You can convert your continuous assignments to simple assignments by making your output a variable. Then move your code into an always block.

module my_mod(
input wire [3:0] A, 
input wire [3:0] B, 
output reg [4:0] C);

always @(*) if(A>B) begin
  C=A;
end else begin
  C=B;
end
endmodule;

Verilog If statement - Signal is not a Constant

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