-1
module rff_try_1(q,inp,clk);
input clk,inp;
output q;
reg q;

DFF dff0(q,inp,clk);
endmodule

module DFF(q,inp,clk);
input inp,clk;
output q;
reg q;
always @ (posedge clk)begin 
if(clk)begin 
q=inp;
end
end

endmodule

here I'm using two modules but output is not coming I'm trying to make two bit right shift register but 1st i have to make one single bit register but even this is not working

scary_jeff
  • 4,314
  • 13
  • 27
Dipjyoti Das
  • 1

1 Answers1

1

There are several mistakes in the code.

1) The line if(clk)begin and relevant end should be removed, posedge clk already describes trigger condition of the flip-flop.

2) A non-blocking assignment (<=) is required for the sequential logic.

The always block should be as follows:

always @ (posedge clk) begin 
    q <= inp;
end

3) Some simulators don't complain, but signal q should be wire in module rff_try_1.

wire q;

Simulation

I simulated the code (after the modifications) on EDA Playground with the testbench below. Used Icarus Verilog 0.9.7 as simulator.

module tb();

  reg clk = 1;
  always clk = #5 ~clk;

  reg  inp;
  wire q;

  rff_try_1 dut(q, inp, clk);

  initial begin
    inp = 0;
    #12;
    inp = 1;
    #27;
    inp = 0;
    #24;
    inp = 1;
  end

  initial begin
    $dumpfile("dump.vcd"); $dumpvars;
    #200;
    $finish;
  end

endmodule

The signal q is as expected as seen on the waveform.

enter image description here

  • thank you sir for your suggestion but i tried what u have said but my output still not showing anything !! i'm giving clock value to the clk and constant 1 to inp. you can check the code in your pc ! may be it will not show anything – Dipjyoti Das Nov 16 '17 at 13:25
  • @DipjyotiDas Could you add your testbench to the question, thus I can reproduce the issue? –  Nov 16 '17 at 13:29
  • we are using force clock to the clk and force constant to inp in xilinx and getting no output in q,does your pc showing any output?? – Dipjyoti Das Nov 16 '17 at 13:50
  • @DipjyotiDas I simulated the code with my testbench, it gives the expected output. I will update the answer. –  Nov 16 '17 at 15:14
  • @DipjyotiDas You may use the simple testbench above instead of forcing the signals. –  Nov 16 '17 at 15:41