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I am making circuits in UPPAAL using basic gates. For this, I instantiate these gates in system declaration to make required circuit. I declared I/O of gates in parameter section and then instantiate these parameter values with required I/O variables in system declaration to make a particular circuit.

let suppose suppose i want to make full adder from 2 Xor,2 And , 1 Or gate. when i run simulation, any one of gate start randomly without following circuit sequence, i-e some time Or simulate first, 2nd Xor simulate first. In order to avoid this i declare some communication channels, and some variables and add these channels and variables in parameters section so that gates simulated in a fix sequence. But after adding channels and variables , i suffer with error- "memory exhausted".

In model-checker Nusmv, if we instantiate smaller modules in a main module, we can also write some code in main along with instantiation, which minimizes number of variables in module instantiation. can we do similar in uppaal. Is there any way to instantiate one template into other. or any hint for making circuits from basic gates without suffering memory error or with minimum parameters. am I adopting right technique for making big circuit from smaller circuits. I used GUI based uppaal. Thanks for your time and help

Qurat
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    could you post some example? A common misconception with Uppaal is to expect ASAP semantics. The "random" behavior you see is actually non-determinism and the verifier will explore all those permutations which can be too many. Synchronous communication via channels help reduce the non-determinism, so it is not clear where the state explosion is. Templates can share global variables directly or through arguments. Are the variables bounded? e.g. some counter may run into infinity and thus memory exhausted. Did you read the tutorial? – mariusm Oct 24 '17 at 12:56
  • I have added code of c-17 circuit made up of 6 nand gates. I instantiated nand gate 6 times to make c-17 circuits with some communication channel and variables declared declare in parameters terms. – Qurat Oct 24 '17 at 19:07
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    I have added code of c-17 circuit made up of 6 nand gates. I instantiated nand gate 6 times to make c-17 circuits with some communication channel and variables declared in parameter section of a template. if I remove or reduced the terms in a parameter section then uppaal does not show memory exhausted error and check the properties quickly utilizing minimum RAM but all 6 nand gates running randomly. – Qurat Oct 24 '17 at 19:15
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    1) your model doesn't have any clocks, no control of time (uncontrolled non-determinism), every non-committed location can spend infinite amount of time -- is that intended? 2) variables like delay_nand_t1 are assigned some values but their values are never used and thrown away, basically they pollute the state space (see active variable reduction in tutorial), consider removing them, or replace by a function if you still want to check their values. So overall in this model anything goes and anything can happen, yet the number of variables is too large, resulting in huge state space. – mariusm Oct 26 '17 at 06:47
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    Also, when modeling some data flow it is quite usual to abstract away from the data values. Your model generates some values (non-deterministically -- it seems that concrete values do not matter), it uses to compute delay_nand and xout_nand, but xout_nand does not seem to be used. I might be wrong: if they are used, then they are overwritten by non-deterministic generation, but then the locations allow infinite delay, thus the values can be overwritten again -- is this the intended behavior? It seems to generate every possible combination, thus state space explosion. – mariusm Oct 26 '17 at 07:45
  • ok. Thankyou Sir – Qurat Oct 26 '17 at 13:05

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