I am quite new to Verilog and trying to learn by writing the DSP blocks that I need for my work.
I am trying to write the variables of sub-modules to a txt/m file to use in matlab.
The top block is TB and the sub-module instance is named "sync_short_inst" as follows:
I am writing three variables in three different file: two variables from top block and one variable from sub-module, as copied at the end of this thread.
I am having problem writing the variable from sub-module in the file. The code compiles without error but when I run simulation, I get error and I don't get anything inside the file. when I comment the third $fwrite, the simulations has no problem but third $fwrite generates following error.
I would appreciate if someone could advice me how to fix the problem.
`timescale 1ns / 1ps
module TB( );
`include "common_params.v"
reg clock;
reg reset;
reg enable;
reg set_stb;
reg [7:0] set_addr;
reg [31:0] set_data;
reg signed [31:0] data_in;
reg input_strobe;
wire short_preamble_detected;
// RAM
//localparam RAM_SIZE = 1<<132;
reg [31:0] FileData [0:10000]; // 10000 words of size 32
reg [31:0] addr1;
integer fID_i, fID_q, fID_mag_sq_av;
`define SAMPLE_FILE "SampleFile.txt"
sync_short sync_short_inst(
.clock(clock),
.reset(reset),
.enable(enable),
.set_stb(set_stb),
.set_addr(set_addr),
.set_data(set_data),
.sample_in(data_in),
.sample_in_strobe(input_strobe),
.short_preamble_detected(short_preamble_detected)
);
initial
begin
$display("Reading memory from...");
$display(`SAMPLE_FILE);
$readmemh(`SAMPLE_FILE, FileData);
$display("Done.");
clock = 1'b0;
reset = 1'b1;
enable = 1'b0;
input_strobe = 1'b0;
# 20
reset = 1'b0;
enable = 1'b1;
set_stb = 1;
# 20
set_addr = SR_SKIP_SAMPLE; // do not skip sample
set_data = 0;
input_strobe = 1'b1;
# 20 input_strobe = 1'b0;
# 20 input_strobe = 1'b1;
end
always @(posedge clock)
begin
if (reset)
begin
data_in <= 0;
input_strobe <= 0;
addr1 <= 0;
end
else if (enable & input_strobe)
begin
data_in <= FileData[addr1];
addr1 <= addr1 + 'd1;
$fwrite(fID_i,$signed(TB.data_in[31:16]),"\n");
$fwrite(fID_q,$signed(TB.data_in[15:0]),"\n");
//$fwrite(fID_mag_sq_av,$signed(TB.sync_short_inst.clock),"\n");
$display($signed(TB.sync_short_inst.clock));
end
end
always #5 clock = !clock;
initial
begin
fID_i =$fopen("IO_Files/file_i.m"); $fwrite(fID_i,"x=0; z=0; i=[... \n");
fID_q =$fopen("IO_Files/file_q.m"); $fwrite(fID_q,"x=0; z=0; q=[... \n");
fID_mag_sq_av= $fopen("IO_Files/file_mag_sq_av.m"); $fwrite(fID_mag_sq_av,"x=0; z=0; i=[... \n");
#80000
$fwrite(fID_i,"]; clear x, clear z");
$fwrite(fID_q,"]; clear x, clear z");
$fwrite(fID_mag_sq_av,"]; clear x, clear z");
$fclose(fID_i);
$fclose(fID_q);
$fclose(fID_mag_sq_av);
end
endmodule
