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Let say I have a hyper-threaded processor and OS sees them as two different virtual processors vp1 and vp2. Now in an LWP1 on vp1, I disable hardware interrupt interrupts. Does not it amounts to say that both of the virtual processors wont get any interrupts unless enabled? And if this is true it should also mean that enabling the interrupts back by another LWP2 on the other processor vp2 will enable interrupts on vp1 as well? I am assuming that disabling interrupts from kernel, only disables it on local processor.

Please explain how this works.

ultimate cause
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  • Processor (core) has only one (two on some architectures) pin for interrupt signal. (Okay, NMI is a separate case). Are you talking about exceptions? Or what *certain* means? – 0andriy Oct 04 '17 at 09:30
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    What is an LWP? Anyway, interrupts can be disabled at the `eflags` level, LAPIC level, interrupt controller level (IOAPIC or PIC) and device level. The first two are resource replicated for each core, so those levels are per core. The interrupt controllers can serve the whole set or a subset of logical processor, so disabling an interrupt there may affect multiple cores (usually all of them for desktop/mobile configurations). At the device level, interrupts are disabled for any agent since this "removes" the source altogether. Explaining the x86 interrupt subsystem is too broad for an answer. – Margaret Bloom Oct 04 '17 at 09:33
  • Edited my question - for better understanding, but I do not mean exceptions, I meant interrupts from hardware devices like ethernet card etc. LWP is Light Weight Process, a scheduled entity on OS, inside kernel. – ultimate cause Oct 04 '17 at 10:22
  • Amend: in my previous comment I spoke of "cores", I meant "threads" (i.e. logical processors). – Margaret Bloom Oct 04 '17 at 11:08
  • @0andriy: You mean per socket / package, not core, right? https://en.wikipedia.org/wiki/Message_Signaled_Interrupts provide 224 interrupts. Even without that, old-school PCI (not PCIe) had at least 4 IRQs that different PCI slots could use. – Peter Cordes Oct 04 '17 at 16:37
  • @PeterCordes, interesting... The question you asked makes sense, the rest doesn't (we are talking about CPU interrupts AFAIU). – 0andriy Oct 04 '17 at 21:21
  • @0andriy: [`cli`](https://hjlebbink.github.io/x86doc/html/CLI.html) stops the core from asynchronously taking interrupts (other than NMI) until you run `sti` to re-enable the `IF` flag in `EFLAGS`. "Clearing the IF flag causes the processor to ignore maskable external interrupts". This lets the kernel defer interrupts until after a critical section. (On a UP CPU, this actually works as a critical section in the multithreading sense.) – Peter Cordes Oct 04 '17 at 21:25
  • @PeterCordes, yes, and what is incorrect in my initial comment then? – 0andriy Oct 04 '17 at 21:26
  • @0andriy: This happens on a per-core basis. If one core runs `cli`, that doesn't stop other cores from receiving interrupts from a NIC, or timer interrupts, or anything else. Your comment seems to be saying that the whole package/socket only has one interrupt pin, and that this is relevant to the question. It isn't, because interrupts get mapped to cores before the `IF` state of a given core is checked. See https://serverfault.com/questions/513807/is-there-still-a-use-for-irqbalance-on-modern-hardware for example about `irqbalance`. If that's not what you meant, please clarify. – Peter Cordes Oct 04 '17 at 21:30
  • @PeterCordes, Ah, I'm an oldschool guy, I'm talking about CPU cores pins, and not SoC ones. That makes confusion. Yes, I know that modern CPU cores are often integrated with LAPIC and alike IPs. – 0andriy Oct 04 '17 at 21:36
  • @0andriy: A single-core hyperthreaded CPU (like Pentium4) still "looks like" a multicore CPU with integrated LAPIC. This question *inherently* requires this, because it's talking about multiple logical CPUs in one package (because that's what hyperthreading is). I'm pretty sure they don't make x86 CPUs without an integrated LAPIC anymore, except maybe 8086 microcontrollers (which are apparently still a thing). – Peter Cordes Oct 04 '17 at 21:41
  • @PeterCordes, so, and LAPIC is connected how to interrupt logic in CPU core? Roughly LAPIC just a simple logic that tells CPU core that *hey, there is an interrupt from somewhere, handle it!* I actually don't get what you want me to do. – 0andriy Oct 04 '17 at 22:01
  • @0andriy: I'm getting out of my depth here, I mostly use asm for optimizing user-space, not for writing IRQ handlers or programming APICs. I'm not asking you to do anything, just explaining why I don't think your comment is relevant. As far as I understand it, once the OS programs the LAPIC/IOAPIC/whatever to distribute interrupts to cores, logically what happens is that interrupts are delivered to logical cores independently of each other. In a modern CPU, it doesn't really matter how the silicon implements the IO registers that let you program the APIC, but it's not just wires "pins". – Peter Cordes Oct 04 '17 at 22:19
  • @PeterCordes I can disagree with you. CPU core by architecture takes signals. One of the signal is interrupt line from LAPIC or any other source. CLI command, which you referred earlier to, basically gates that wire (in simplified model). See above comment from Margaret. – 0andriy Oct 04 '17 at 22:22
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    @0andriy: ok, that makes sense as a mental model without HT. But Intel's Hyperthreading gives each logical core on a physical core its own logical "wire". I guess physically/electrically there might be two actual wires, each one gated by the `IF` of one logical core. `cli` and `sti` are serializing, IIRC, so the CPU doesn't need to track the IF state during out-of-order execution. But more likely the interrupt number is sent directly to the logical core instead of raising an interrupt and then having it request the interrupt number from somewhere so it can index the IDT. – Peter Cordes Oct 04 '17 at 22:38

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The two logical cores of a hyperthreaded processor have their own APIC IDs, so as far as interrupts are concerned they are separate CPUs. (In Knight's Landing / Xeon Phi, four logical cores)

This makes it possible to disable interrupts on any one logical core independently of anything else, using cli / sti in kernel mode. Everything is exactly the same as on a non-SMT multi-core system, because that's how hyperthreading is designed to work.

Anything else would be inconvenient and weird, and increase latency for the other logical core by sometimes disabling the interrupts it was waiting for, so it's pretty clear that this is the sane way for Intel to have designed it.

Peter Cordes
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