Verilog: Even parity for input A

Question

The following code obtains the even parity for the input A. (i.e. parity = 1 if A contains 0 1’s or an even number of 1’s)

reg [7:0] A; 
wire parity;
assign parity = ~^A;

How will I use a for loop in a procedural block to obtain the same function

you should provide your own attempt of doing so. – Serge Sep 16 '17 at 23:22 — Serge, Sep 16 '17 at 23:22

score 1 · Accepted Answer · answered Sep 19 '17 at 18:03

Something like this should work. Basically what you want to do is start at one end of the vector and work your way to the other end. Flipping the parity bit anytime you spot a '1'. If you don't spot any, parity is 1. If you spot an even #, parity will be 1 as well.

integer i;
reg parity;

always (*) begin
    // Default values
    parity = 1'b1;

    for (i = 0; i < 8; i++)
        if (A[i])
            parity = ~parity;
end

Verilog: Even parity for input A

1 Answers1