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I want to know how VIC can handle the external interrupts efficiently

user559208
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    Who's VIC? An interrupt controller is not defined by the ARM7 core, it is a vendor specific external peripheral device. Moreover, what is your question about, how the hardware works or how to work with the hardware? In either case the answer is read the vendors data-sheet/reference manual. – Clifford Jan 05 '11 at 17:01
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    @Clifford: VICs are common enough on ARM7 devices that I think the tag isn't out of line (is there an available ARM7 device that doesn't have a VIC?). And, by itself, the fact that RTFM would answer a question doesn't necessarily mean a question isn't appropriate for SO; I think the vast majority of questions here could be answered by reading docs. – Michael Burr Jan 07 '11 at 17:30
  • @Micheal Burr: That is not what I am saying. Rather that *Vectored Interrupt Controller* is a generic term, what one vendor implements is not necessarily the same as another vendor's implementation. Others may implement an interrupt controller and use another term entirely. The point is that the interrupt controller is not defined by ARM. – Clifford Jan 07 '11 at 20:14
  • ARM defines an interrupt controller caled PrimeCell VIC, its use is optional and many vendors use an alternative implementation (ST's STR7 EIC for example). NXP parts use the PrimeCell implementation, perhaps we can assume the question is referring to this, but nonetheless knowing the exact part would allow a better targetted answer. – Clifford Jan 07 '11 at 22:34

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A little background (you tagged "arm7" so presumably this question isn't about the Cortex NVIC, etc..)

Initially, ARM processors supported 2 types of interrupts: normal interrupts (IRQ) and Fast Interrupts (FIQ). Each peripheral which could interrupt the CPU would either trigger an IRQ or a FIQ. IRQ has a single vector, FIQ has a single vector.

Sometimes the mapping from peripheral to IRQ/FIQ is done in hardware, sometimes it's configurable. But the point is that as soon as you have >2 peripheral interrupts, they have to share an interrupt vector. In other words, if you have 3 interrupt sources, you are guaranteed at least one of IRQ or FIQ will be used by multiple devices. This implies that when you take the interrupt, you have to "poll" (usually hardware registers) to find out "why am I here? who interrupted me?"

The whole idea of the VIC is that each interrupt has its own unique vector, so that when you vector to that interrupt slot, you know exactly who is interrupting you. No polling "OK, who interrupted me?"

There is a lot more information about the ARM VIC (and its many variants) at ARM's site, including configuration info, register definitions, nested/prioritized interrupts, etc. but your question asked specifically about how the VIC handles interrupts efficiently. Describing every detail of its features is way outside the scope of this question.

(I interpreted "efficiently" as "with as little polling/interrogating as possible". Note that prioritized interrupts, also supported by the VIC, reduce the latency of high-priority interrupts, and that might also be considered "more efficient", although I don't really put it in the same category as not having to poll "who interrupted me?")

More info on the Primecell VIC can be found here at ARM's site.

Dan
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