Align parentheses in verilog-mode (Emacs)

Question

My question is related to Modify verilog mode indentation but slightly different. In verilog-mode, when opening and closing parentheses are on different lines, the closing parenthesis is always one space behind (to the right of) the opening parenthesis. For example:

module aurora_64b66b
  #(
    parameter DATA_WIDTH=170,
    parameter CNT_WIDTH=8,
    parameter SHIFT_DIRECTION=1
    )
   (
    input                      RESET,
    output                     USER_CLK,
    output reg                 data_out,
    output reg                 load_sr,
    output reg [CNT_WIDTH-1:0] count_delay
    );

   (
    )
   {
    }

I would like the closing parenthesis to be exactly aligned with the opening one. I cannot figure out a way to do this by setting a few variables for verilog-mode.

I had the same problem in vhdl-mode for the parentheses around ports but I could do

(defun vhdl-lineup-arglist-offset (langelem)
  "vhdl-lineup-arglist minus the basic-offset"
  (- (vhdl-lineup-arglist langelem) vhdl-basic-offset))
(vhdl-set-offset 'arglist-close 'vhdl-lineup-arglist-offset)

to get the effects I wanted. Is there an equivalent solution in verilog-mode?