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In the book "The Intel Microprocessors" by Barry B. Brey, I have seen that if the segment address is FFFFH, A20 pin is enabled while adding offset to the segment address. But to take the full advantage of the "high memory", any segment address in the range F001H to FFFFH (value stored in the segment register) should do the same.

So if the value in the segment register is F001H and the offset is FFFFH, the actual address should be 10000FH if the A20 pin is enabled. But if it is disabled, the actual address will be 0000FH.

Is the A20 pin enabled for any segment address in the range F001H to FFFFH? Or the pin gets enabled for only FFFFH in the segment register?

Preetom Saha Arko
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  • The A20 pin isn't asserted (enabled) for a particular range of segment register values. It is either on or off (some modern CPUs no longer allow you to turn off the A20 pin). There is an exception though. When a 386 processor powers up the A20-A31 lines are tied high (asserted) until the first intersegment jump or call is done (effectively until CS segment is changed) at which point they are all brought low (zero). This allows the BIOS entry point to be placed just under the 4gb mark rather than under the first megabyte. – Michael Petch Aug 11 '17 at 18:09
  • With the A20-A31 trick mentioned above (modern processors may do an equivalent thing but a different mechanism) the processor starts out with a _CS_ segment of F000 and offset of FFF0. Normally that is physical address 0xFFFF0 but since at power on the upper 12 address lines are tied high the actual physical memory location accesses is 0xFFFFFFF0 . This remains the case until the _CS_ segment is changed with a intergement (far) jump or call at which time A20-A31 go back to a zero state. – Michael Petch Aug 11 '17 at 18:14
  • So to answer your question. With the exception right after power on before an intersegment(far) jump or call that changes _CS_ the A20 pin is either on or off. It doesn't vary based on the value in the segment register. – Michael Petch Aug 11 '17 at 18:21
  • On a side note. One of the prevalent mechanisms (almost always the case) is to make it appear the A20-A31 pins are high at power on is that many 386 processors set the CS descriptor cache base value to 0xFFFF0000. It surprises many that the actual value in the visible _CS_ segment register in real mode isn't used. When _CS_ is set there is a hidden base computed and placed in the descriptor cache that are used for further computations. At bootup the 0xF000 in _CS_ isn't relevant. At power on init the offset 0xFFF0 is added to the hidden base value of 0xFFFF0000 which ends up being 0xFFFFFFF0. – Michael Petch Aug 11 '17 at 18:28
  • @MichaelPetch i think you should probably turn that into an answer – Grady Player Aug 11 '17 at 18:34
  • The key is "full advantage". You only get the maximum addressable upper memory (64KB - 16) if the segment register is 0xffff. Little point in using another value. – Hans Passant Aug 11 '17 at 19:03
  • @HansPassant Well in unreal mode (DS/ES/SS descriptor cache limit set to 0xffffffff) you can offsets higher than 0xffff. – Michael Petch Aug 11 '17 at 19:23

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