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Can I assign something like this in Verilog: 

reg [4:0] synd[0:4]={s0,s1,s2,s3,s4};//s0,s1,s2....s4 are 5 bit values.

Also, while accessing this array from inside the 'always' block, should I just reference it as say synd[0] for s0 and so on?

Shankhadeep Mukerji
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Sushrut Kaul
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  • in verilog -- no, in system verilog -- yes (just a bit different syntax). In any case such initialization of variables is not synthesizable. In the code you use synd[index] to access the array. – Serge Aug 10 '17 at 18:06
  • Syntax in SystemVerilog is exactly correct. – dave_59 Aug 10 '17 at 18:59
  • Possible duplicate of [Way to initialize synthesizable 2D array with constant values in Verilog](https://stackoverflow.com/questions/14130181/way-to-initialize-synthesizable-2d-array-with-constant-values-in-verilog) – Qiu Aug 11 '17 at 06:32

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Verilog does not allow for more than 1-D array. However systemverilog allows such construct and it is syntactically correct according to systemverilog.

Shankhadeep Mukerji
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