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Cortex M3 processor has two stack pointer: PSP, MSP. In some complex applications, user program use PSP pointed to user program stack. Exception handler use MSP pointed to main stack.

The question is: There is a interrupt happened when user program is running. Before entering into the interrupt handler, the R0-R3, R12, LR, PC, and xPSR registers would be pushed into stack. But which stack is used to store these registers ?

artless noise
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lrouter
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  • sometimes they have two stack pointers, not sure on the m3 but some of the cortex-ms it is a compile time option. And using the second stack pointer is painful at best, unless you are specifically trying to use it you are sharing one stack. trivial to see if you copy/dump the stack in a handler then examine it... – old_timer Aug 02 '17 at 13:31
  • Os use main stack, user program use program stack. Some simple application will only use MSP (main stack). – lrouter Aug 02 '17 at 13:34
  • The stack pointer, SP, banks SP_main and SP_process. The current stack depends on the mode and, in Thread mode, the value of the CONTROL.SPSEL bit, see The special-purpose CONTROL register on page B1-575. A reset selects and initializes SP_main, see Reset behavior on page B1-586. – old_timer Aug 02 '17 at 17:35
  • right there in the arm docs, will let you read the rest – old_timer Aug 02 '17 at 17:36
  • are you answering your own question or at least trying to? Confused. You cant always use the second stack, if you have ever tried to use it you may find out why you might not want to use it or more importantly it doesnt at all work like you think it does, and why are you asking this question if you already have an answer in your mind as to how it works? – old_timer Aug 03 '17 at 02:43
  • @old_time You have answered my question. I have get the correct answer based on all your answers. Thanks for your help. I have told you in my system there is a Os. – lrouter Aug 03 '17 at 03:29
  • having an os doesnt mean anything, you have to look at the specific os in question to see if they have chosen to use this feature. Not having an os and running baremetal you are also free to use this feature or not. having an os does not answer the question, is the feature enabled or not and the pointer initialized answers the question (along with other code required to support this feature). – old_timer Aug 03 '17 at 20:06

1 Answers1

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According to my reading of the ARM documentation (Cortex-M3 Devices Generic User Guide), register stacking upon exception entry happens on the current stack and the processor then enters Handler mode. If you think about it, this is the most convenient behavior for ordinary circumstances.

andy mango
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  • So it will program stack when the processor enters into exception handler from user program. At the end of exception handler, it will pop out the program stack and return to thread mode. – lrouter Aug 03 '17 at 02:11
  • Again if you read the docs, the processor stores an EXC_RETURN value to the link register (LR) and uses this value to know when exception processing has ended and to which processor mode execution continues. So in the case of taking an exception from Thread mode, under normal circumstances, the return from exception places you back in Thread mode and the Thread mode stack pointer is used to restore the registers. Note that operating systems and context switches implied by OS tasks can change this sequence to meet their needs. – andy mango Aug 03 '17 at 15:48