I want to create AWGN channel in VHDL testbench. Is it possible? and how can I proceed? I searched online but not many related posts.
Regards
I want to create AWGN channel in VHDL testbench. Is it possible? and how can I proceed? I searched online but not many related posts.
Regards
Yes, you can.
How to generate a uniform distributed value in VHDL is described here. Quote (original by "Vipin Lal"):
library ieee;
use ieee.math_real.all;
entity rand_gen is end rand_gen;
architecture behavior of rand_gen is
signal rand_num : integer := 0;
begin
process
variable seed1, seed2: positive; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 1000.0; -- the range of random values created will be 0 to +1000.
begin
uniform(seed1, seed2, rand); -- generate random number
rand_num <= integer(rand*range_of_rand); -- rescale to 0..1000, convert integer part
wait for 10 ns;
end process;
end behavior;
Then you have to scale the output of the uniform function to a AWGN distribution. An example in C is given here. Quote(summarized from original by "Dr Cagri Tanriover")
temp2 = ( rand() / ( (double)RAND_MAX ) );
temp1 = cos( ( 2.0 * (double)PI ) * rand() / ( (double)RAND_MAX ) );
result = sqrt( -2.0 * log( temp2 ) ) * temp1;
Just correctly convert this to VHDL. The math_real
library contains all functions and constants required.