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For personal research, I want to compare the performance of two microprocessor: Intel 8051 and Sparc Leon3. In order to evaluate these, an execution of a set of some representative functions is done through an ISS (Instruction Set Simulator). Then, I collect statistics and trivially reason about data figured out from the simulation.

Since the core of the 8051 microcontroller that I'm using as reference does not have external memory neither a cache, I want to disable the instruction cache and the data cache on the Leon3 to obtain comparable data with those of the first one.

I'm using TSIM for the simulation of Leon 3. I read on the data sheet that this use a control register to set the behaviour of the cache. So I added an inline assembly instruction, to functions used in benchmark, that writes in this register and sets the cache to disable. I'm sure that the bits in the register are changed but when I do the simulation I see the caches written. I can see this because of commands that I can tell to simulator.

I'm here to ask if you can help with this problem or you have some ideas because I'm stuck.

vnzstc
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    I don't quite see what crippling one of the contender proves, and the classic 8051 MCU _does_ have an external memory bus (while modern implementations frequently have limited FLASH caches). Generally speaking the SPARC excels in complex and computationally-expensive workloads and as a high-level language target, while the strength of a modern 8051 lies in low-power and low-latency applications as well as its low gate count (as in size/area). Really though, they are targeting different markets and would be highly unlikely two be contending choices for a real-world application. – doynax Jul 08 '17 at 11:43
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    what kind of simulator is going to give you cycle accurate results? Is this an rtl (verilog/vhdl) tool? I also dont understand the point of this exercise, some massive high end processor (not an mcu) vs a classic mcu, its like a semi truck vs a pickup truck, both have pros and cons, but cant really compare them to each other in any sort of competition. – old_timer Jul 08 '17 at 11:52
  • this could be more of a simulator question than a processor question. what if in the bootstrap you simply dont launch the main code and stay in a loop or do some memory accesses, is the simulated cache being accessed then? if so then perhaps the simulator is to far from reality to use for any kind of performance measurement task. – old_timer Jul 08 '17 at 11:55
  • " They are targeting different markets and would be highly unlikely two be contending choices for a real-world application. " In my opinion, this is an interesting thing. Taking into account the markets, which microprocessors can I compare? I am interested to learn more about the 8051 and Leon3 market. Do you have any source? Also, I would be happy if you have sources about microprocessors and their market, so I can deeply think about the choice. I think that it is a useful research to do for embedded system designers which must choose between microprocessors in early phase of the design. – vnzstc Jul 08 '17 at 12:10
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    Since the cache is one of the architectural differences that makes it faster, why does disabling it make the test "comparable". You may as well ask how or disable the upper 24 bits of the data bus to make it 8 bit like an 8051. What you are comparing is a Trabant with a Ferrari. Leon3 has 1.4 MIPS/MHz, while _modern_ 8051 is <1 DMIPS/MHz (original 8051 required 12 clocks per instruction so were <.1 MIPS/MHZ). – Clifford Jul 08 '17 at 16:38
  • @No one is thinking "which shall I use Leon3 or 8051?" Other design factors make that decision for you; you hardly need a performance comparison to determine. Leon3 vs NIOSII or vs ARM perhaps, but there is little point in comparing it to an 8051. Why have you selected these for comparison - are they the choices you have for soft-cores on an FPGA? I suggest that the choice between these would not be based on performance rather than gate count. You choose an 8051 when it is _enough_ because it is _tiny_. You choose LEON3 when you need 32bit performance and/or need a large address space. – Clifford Jul 08 '17 at 16:51

1 Answers1

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I haven't use TSIM but I tested actual leon3 hardware with below code.

It may not what you want, but I hope you can compare your code with mine to disable cache correctly at least :)

I_cache_disable() {
  asm(" set 0x0c, %g1;");
  asm(" sta %g1, [%g0] 2 ");
}

D_cache_disable() {
  asm(" set 0x03, %g1");
  asm(" sta %g0, [%g0] 2 ");
}

I hope this code could be helpful

I.C.Baek
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    That clobbers some `%g` registers without telling the compiler about it, and also both instructions need to be in the same statement if you want to be sure the compiler doesn't choose to reorder them with surrounding code and emit instructions that use or depend on those registers between the `asm` statements. – Peter Cordes Oct 22 '21 at 07:21