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When I go to simulate my top-level module in Xilinx Vivado 2016.4, I receive the peculiar error:

ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [<...>/header.vh]

I am using the built-in Vivado Simulator with Verilog 2001 specified. My header.vh looks like the following:

`ifndef _header_vh_
`define _header_vh_

    function integer clog2;
        input integer value;
        begin 
            value = value - 1;
            for (clog2 = 0; value > 0; clog2 = clog2 + 1)
                value = value >> 1;
        end 
    endfunction

`endif
craymichael
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1 Answers1

4

This error arises as the scope of the function, clog2, is effectively set to root (as it's not declared within a module); this scope declaration is not allowed in Verilog 2001, but is in later versions (e.g. SystemVerilog). Switching to SystemVerilog would solve the issue (but is not recommended), but introducing a module wrapper for the function will suffice.

`ifndef _header_vh_
`define _header_vh_

module header();
    function integer clog2;
        input integer value;
        begin 
            value = value - 1;
            for (clog2 = 0; value > 0; clog2 = clog2 + 1)
                value = value >> 1;
        end 
    endfunction
endmodule

`endif
craymichael
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  • 2
    from the methodology point of view, declaring functions and anything else in the root scope will cause issues in projects due to possible name collisions between different parts and ips. So, do not do it, always wrap it in a module or in a system verilog package. – Serge Jul 08 '17 at 00:03