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I know what are both locality principles and pipelining techniques. But I can't see any sort of interconnection between the two things.

How can locality principles impact pipelining techniques?

emarkk
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  • I'm voting to close this question as off-topic because it is not going programming question. It is a CPU design question. – Raymond Chen Jun 24 '17 at 21:21
  • Don't close it, it's a CPU architecture question, there is a tag for it in SO and the question is tagged appropriately. – Isuru H Jun 24 '17 at 21:52
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    @IsuruH, It may be on topic, but it's too broad, and as it currently is - unanswerable. In general, questions like "What's the connection between A and B" tend to be problematic. – Leeor Jun 27 '17 at 20:13
  • If you just mean how to pipeline given that cache misses are possible, then a buffer/queue between instruction-fetch and decode can prevent bubbles due to I-cache misses. Similarly, a store buffer hides the latency of cache-miss stores. – Peter Cordes Jul 10 '17 at 01:41

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One case I could think of is the instruction cache hit during IF stage. Spatial locality is likely to increase instruction cache hits when there is less flow control. Also when there is flow control, like a loop, temporal locality will increase the hit rate of the instruction cache. If the IF is not succeed due to a cache miss, pipeline has to be stalled, which can be solved by locality principles.

Isuru H
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  • None of these arguments are specific to pipelining. The same thing applies to instruction fetch in a non-pipelined CPU. You also haven't pointed out anything you'd do differently when designing a pipelined CPU if locality wasn't an issue. (The question is just way too broad. It's not clear if it's just asking about accounting for the possibility of cache misses, or something more specific. If the former, then put a buffer between fetch and decode so fetch stalls may not create bubbles in the rest of the pipeline.) – Peter Cordes Jul 10 '17 at 01:40