Can someone explain this about paging in operating system?

Question

Frequently, on a 32-bit CPU, each page-table entry is 4 bytes long, but that size can vary as well. A 32-bit entry can point to one of 2^32 physical page frames. If frame size is 4 KB (2^12), then a system with 4-byte entries can address 2^44 bytes (or 16 TB) of physical memory. We should note here that the size of physical memory in a paged memory system is different from the maximum logical size of a process.

How does paging make logical memory space more than physical memory space? Isn't total number of frames in 32-bit CPU equal to 2^(32-12)=2^20 number of frames rather than 2^32 number of frames? If so, isn't a system with 4-byte entry capable of addressing (2^20)*(2^12) bytes of memory?

Number of frames in memory is `memory-size\page-size`. If you have a 4GB main memory, then you will have `2^20` frames. Besides that, your question is too broad. — Tony Tannous, Jun 05 '17 at 06:07
This is exactly the same question I wanted to ask! This paragraph in the book is indeed confusing. — desa, Nov 08 '18 at 14:25

score 4 · Accepted Answer · answered Jun 06 '17 at 11:20

That text isn't very clear admittedly. I'll try to clear it out.

When translating a virtual address into a physical one, a fixed number of lower bits don't get translated:

+---------------------+----------+
|    High bits        | Low bits |
+---------------------+----------+
         |                  |
         |                  |
         V                  |
   [Page tables]            |
         |                  |
         |                  |
         V                  V
+---------------------+----------+
|        Physical address        |
+---------------------+----------+

The lower bits number is tied to the page size: if we assume 4KiB pages then the lower 12 bits are fixed and not translated.
We also assume that the virtual address space is 32 bits.

If a page table entry is 32-bit long it can give 32 bits to use as the high part of the physical address.
Thus we have 20 (32 - 12) bits in input and 32 bits in output when looking up the page tables.
With the additional 12 bits from the fixed part this gives 32 + 12 = 44 bits of physical address.

An updated figure:

        <---------- 32 bits ----------->
        <---- 20 bit -------> <- 12 b -> 
       +---------------------+----------+
       |    High bits        | Low bits |
       +---------------------+----------+
               |                  |
               | 20 bit           |
               V                  |
         [Page tables]            |
               |                  |
               | 32 bit           |
               V                  V
+----------------------------+----------+
|           Physical address            |
+----------------------------+----------+
 <-------- 32 bits ---------> <- 12 b ->
 <------------- 44 bits --------------->

This is not a true 44-bit addressing however, pointers are still 32-bit.
Application can only access 4GiB of memory directly, but the OS can map an application to the first 4GiB, another to the second 4GiB and so on.

This is similar to how PAE works on x86.

The assumption that all of a page table entry is used to give the higher bits of the physical address is untrue.
Some of the bits are used to set the attribute of the frame: cache-ability, access right, mapping status and so on.

The higher bits of the physical address are called page frames.
The number of page frames is determined by the structure of a page table entry, not by the size of the virtual address space (nor of the physical address space).
If a page table entry has 50-bit for the frame number then there are 2⁵⁰ frames.
The lower part of the physical address is called page offset and it is determined by the page size (or frame size, they are equal by design).

Just to make sure that I understand it correctly. Does it mean that even if we can use one page table to point to 44-bit physical addresses, some frames in the physical memory (2^44 - 2^32) will never be references in this page table? However, in another page-table (associated with a different process), we could point to other 2^20 addresses in the physical memory? — desa, Nov 08 '18 at 14:42
@desa Page tables have fixed layout. You can think of them as a mapping function taking a 20-bit input number and outputting a 32-bit number. Along with the lower, fixed, 12 bits this translates a 32-bit address (20+12) into a 44-bit one (32+12). — Margaret Bloom, Nov 08 '18 at 17:14
@MargaretBloom how can the mapping function translate from 20-bit to 32-bit? That means that 2^12 frames cannot be addressed, right? — Bender, May 13 '22 at 10:09

score -1 · Answer 2 · answered Feb 20 '21 at 13:42

-1

When we say that a cpu is 32-bit or 64-bit , what it means is that it can point to 2^32 or 2^64 physical page frames respectively. Now if one page frame is of size 4KB (2^12) then the total amount of memory that can be accessed is (2^12)×(2^32)=2^44 bytes or 16TB

answered Feb 20 '21 at 13:42

kushagra deep

462
6
12

Usually we mean the whole pointer (including the offset-within-page) part is 32 or 64 bits. Some 32-bit CPUs use various ways to expand addressable memory beyond 4GiB, (e.g. page tables with wider physical addresses, like x86 PAE, which doesn't increase the size of one process's virtual address space). I'm not aware of any 32-bit CPU that works as you describe, with 32+12-bit pointers. – Peter Cordes Feb 20 '21 at 23:53

Can someone explain this about paging in operating system?

2 Answers2