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It is easy enough to find the answer for Windows, Linux and OSX on the web, but how about on commercial UNIX operating systems like AIX (on POWER), HP-UX (on Itanium) and Solaris (on SPARC). Experimenting with false cache line sharing code is not the answer I'm looking for.

Edit: Added the CPU architectures.

okun
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If you're trying to optimize performance, then benchmarking is exactly what you should do. For an example, see ATLAS.

If you're not trying to optimize performance, why do you care about the cache line size, and do you also care about the number of lines and the associativity?

What CPU architectures do you need to support?

Ben Voigt
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  • I definitely agree about the benchmarking! What I meant by saying I don't want to experiment with false cache line sharing is that experimentation is not the way I want to find out the cache line size in the product, but would prefer a syscall or even inline asm call. – okun Dec 13 '10 at 16:55
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For Solaris (on both SPARC and x86 architectures) you can use that command:

$ prtpicl -v -c cpu | grep -i cache-line-size
  :l1-dcache-line-size   0x40 
  :l1-icache-line-size   0x40 
  :l2-cache-line-size    0x40
jlliagre
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You can have a look at the hwloc library (BSD license) which gives this kind of information for different systems and architectures. You can either use the command line tool lstopo or the provided API (see documentation).

Etienne PIERRE
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