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I am looking to find the percentage between memory read and write CPU instructions ( including the read instructions to fetch the program ), but I cannot find any such statistics. A plausible quantity could be 1 instruction read, one data read, one data write. So reads compared to write could be 2/1. But it should be higher I suppose ( something like 3/1). Any information on that ?

George Kourtis
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  • This really depends on the sort of task you're performing. Summarizing an array or doing a dot product is all reads, copying data is more like 1:1, etc.. – Leeor May 14 '17 at 19:22
  • That is obvious, but there should be a "mean" user statistic regarding desktop office use e.g. . Something at least to be able to think of. – George Kourtis May 14 '17 at 19:24

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Hennessey and Patterson's Computer Architecture: A Quantitative Approach provides statistics for five SPEC CPU2000 integer benchmarks (gap, gcc, gzip, mcf, perlbmk) for MIPS:

           % loads   % stores
gap           26.5      10.3
gcc           25.1      13.2
gzip          20.1       5.1
mcf           30.3       4.3
perlbmk       28.7      16.2

As you can see, a decent rule of thumb is about a quarter of instructions are loads and there are half as many stores as loads.

You can also see that even among integer workstation benchmarks, there is significant variation.

What you cannot see from these statistics is the influence of ISA and compiler (and optimization level chosen). The availability of complex instructions will tend to reduce the number of instructions executed. A larger number of registers under higher compiler optimization will tend to reduce the amount of memory traffic.

With compiler optimizations the number of instructions executed can be reduced (e.g., loop unrolling can eliminate branch instructions) or increased (e.g., strength reducing a multiplication by a constant into shifts and adds, replacing poorly predicted branches with conditional moves can increase instruction count). Compiler optimizations can also reduce the number of loads and stores (e.g., better register allocation using extended liveness information from link-time code generation or inlining) or increase the number of loads or stores (e.g., using load-and-operate instructions might reduce register pressure allowing software pipelining of a loop to fully hide operation latencies).

BeeOnRope
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  • Thanks, but I downloaded the book and looked fastly ( 700 pages ) and was unable to find the related pages ... Could you help ... – George Kourtis May 15 '17 at 18:07
  • The idea is to know if we make slower writting (e.g. half the speed of reading) the write instructions ( while program reading and data reading remains the same ) what will be the impact on overall speed. As you say it 1/4 are reads 1/8 writes and 5/8 program. In that case the system would delay by only 1/8. – George Kourtis May 15 '17 at 18:09
  • @GeorgeKourtis In the 4th Edition, the table is in Appendix B (Figure B.27). Since writes can be buffered, write speed is typically not critical. –  May 16 '17 at 02:37