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When I edit a VHDL testbench (simulation source) in Vivado (project mode), background syntax checking seems to be disabled: Obvious syntax errors like missing semicolons or undefined signals are not underlined with a squiggly red line (as in all design sources).

Is there a way to activate automatic background syntax checking for test benches? Could there be another reason why some files are not syntax-checked?

Chipmuenk
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    This question might be more suited to the Xilinx forums to be honest. It's not really a coding issue. – scary_jeff May 12 '17 at 09:01
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    You got a point there ... I'll post the question at the Xilinx forum as well and cross-reference answers. If there are no objections here, I'd like to leave the question in SO as well: Lots of my students (and other beginners certainly as well) are unnerved by this issue and they will most likely check SO first. – Chipmuenk May 12 '17 at 09:04

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This seems to be missing feature: Xilinx Forums: No-syntax-highlighting-for-VHDL-testbenches

Chipmuenk
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