Debug output for instruction selection by pattern matching

Question

Running llc --debug, the output for instruction selection pattern matching is quite unreadable on its own. Here's some example output:

ISEL: Starting pattern match on root node: t7: i8,ch = load<LD1[%1](dereferenceable)> t0, t2, undef:i16

  Initial Opcode index to 581
  TypeSwitch[i8] from 590 to 593
  Match failed at index 595
  Continuing at 624
  Match failed at index 626
  Continuing at 662
  Match failed at index 667
  Continuing at 754
  TypeSwitch[i8] from 761 to 764
  Morphed node: t7: i8,ch = LPMRdZ<Mem:LD1[%1](dereferenceable)> t2, t0

What do does numbers mean? How do I use that output? In particular, I'd like to see which instruction patterns were tried (linked to my TargetInstrInfo.td file), in what order, and what sub-patterns matched or failed.

score 0 · Accepted Answer · answered May 07 '17 at 15:45

I've found that the LLVM build process uses Target/MyArch/MyArchInstrInfo.td to generate, among other things, a MyArchGenDAGISel.inc file. The numbers in the debug messages correspond to tags in that file; for example, here's the relevant part for the example in my question. It gives pretty much exactly the kind of information I was hoping for.

/*581*/       OPC_RecordMemRef,
/*582*/       OPC_RecordNode, // #0 = 'ld' chained node
/*583*/       OPC_Scope, 39, /*->624*/ // 3 children in Scope
/*585*/         OPC_RecordChild1, // #1 = $memri
/*586*/         OPC_CheckPredicate, 1, // Predicate_unindexedload
/*588*/         OPC_CheckPredicate, 2, // Predicate_load
/*590*/         OPC_SwitchType /*2 cases */, 14, MVT::i8,// ->607
/*593*/           OPC_CheckPatternPredicate, 0, // (Subtarget->hasSRAM())
/*595*/           OPC_CheckComplexPat, /*CP*/0, /*#*/1, // SelectAddr:$memri #2 #3

/*624*/       /*Scope*/ 37, /*->662*/
/*625*/         OPC_MoveChild1,
/*626*/         OPC_CheckOpcode, TARGET_VAL(AVRISD::WRAPPER),

/*662*/       /*Scope*/ 125, /*->788*/
/*663*/         OPC_RecordChild1, // #1 = $src
/*664*/         OPC_Scope, 88, /*->754*/ // 2 children in Scope
/*666*/           OPC_MoveChild1,
/*667*/           OPC_CheckOpcode, TARGET_VAL(ISD::Constant),

/*754*/         /*Scope*/ 32, /*->787*/
/*755*/           OPC_CheckChild1Type, MVT::i16,
/*757*/           OPC_CheckPredicate, 1, // Predicate_unindexedload
/*759*/           OPC_CheckPredicate, 2, // Predicate_load
/*761*/           OPC_SwitchType /*2 cases */, 10, MVT::i8,// ->774
/*764*/             OPC_CheckPatternPredicate, 0, // (Subtarget->hasSRAM())
/*766*/             OPC_EmitMergeInputChains1_0,
/*767*/             OPC_MorphNodeTo1, TARGET_VAL(AVR::LDRdPtr), 0|OPFL_Chain|OPFL_MemRefs,
                        MVT::i8, 1/*#Ops*/, 1, 
                    // Src: (ld:i8 i16:i16:$ptrreg)<<P:Predicate_unindexedload>><<P:Predicate_load>> - Complexity = 4
                    // Dst: (LDRdPtr:i8 i16:i16:$ptrreg)

Debug output for instruction selection by pattern matching

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