Multiples modules reading same fifo

Question

Is it possible to instantiate multiple modules to read from the same fifo assuming they are not reading at the same time, but take turns??

For example:

int _tmain(int argc, _TCHAR* argv[])
{
    sc_fifo<int> PacketTx(24);
    sc_fifo<int> PacketRx(20);

    Transmit t1("Transmit");
    t1.PacketRx(PacketRx);
    t1.PacketTx(PacketTx);

    Receive r1("Receive1");
    r1.PacketTx(PacketRx);
    r1.PacketRx(PacketTx);

    Receive r2("Receive2");
    r2.PacketTx(PacketRx);
    r2.PacketRx(PacketTx);

    sc_start();

    return 0;
}

score 2 · Accepted Answer · answered Apr 21 '17 at 06:44

It is possible but you need to add synchronization signals to the module's.

For sample implementation closer to your requirement is available under SystemC source code from Accellera SystemC download page.

Download the "Core SystemC Language and Examples" zip file:

Unzip the file.
Navigate into the directory and look for "examples" directory.

Following example are much closer to your requirement:

examples/sysc/pkt_switch/
Note: This example does not use sc_fifo's but utilizes the sc_in/out port's.
examples/sysc/simple_bus/
Note: This example showcase the use-case to model CPU bus model. This example also currently does not utilize the sc_fifo.

But you can get much better ideas for your implementation details.

Multiples modules reading same fifo

1 Answers1