Non-specific `include file name - System Verilog compiler directives

Question

I want to use the `include directive to call upon a non-specific file name. For example, there is this file name "name_defines.svh" in some other directory. Since the "name" of "name_defines.svh" changes(it can be eg, a_defines.svh, b_defines.svh.. etc), is it possible if I just use

`include "_defines.svh"

or

`include "*_defines.svh"

so that the system verilog compiler finds the file name and include it in my current .sv file, just as if I used

`include "name_defines.svh"

p.s. - assume that no other files in the working directory has the trailing "_defines.svh" wordings and is unique to only "name_defines.svh"

Answer 1

SystemVerilog does not have a mechanism to do this. Wildcard file matching is a feature of the shell you are running your simulation from.

If there is only one file you would like to include in your current working directory, it should have the same name. Or, your invoking script can put a link from the specific name to the generic name. Another option is to define the file name with a macro on your command line

+define+FILE="name_defines.svh"

`include `FILE

Note that you may need to escape the quotes on your command line depending on the shell you are using.