2

For electrical net simulation in SV, I'd like to implement a trapezoidal integration method using companion models for caps and inductors. [http://circsimproj.blogspot.nl/2009/07/companion-models.html]

Some simulation tool vendors provide a SV package allowing to solve for the voltages of a resistive network. See Mixed Signal Verification: Model Development by Simetkosky for a published resolution function.

In order to implement the trapezoidal method, I need to synchronously change equivalent resistors and currents:

  • at the beginning of the simulation, a small time step is chosen, every dynamic element is replaced by a resistor.
  • the package resolving function calculates new node voltages.
  • every dynamic element calculates a maximum time step based on tolerance criteria.
  • the next time step is calculated as the minimum of the requested time steps and a (delayed) update signal is issued.
  • once the update signal fires, every dynamic element calculates a new equivalent resistance and current..

The package uses a nettype with the following structure:

package SVA_pkg;
typedef struct {
    real V;
    real I;
    real R;
}  SVAstruct;
function automatic SVAstruct res_SVA (input SVAstruct driver[]);
   // resolution function
endfunction
nettype SVAstruct SVAnet with res_SVA;
endpackage

// in module
inout SVAnet P;
assign P = '{1 , 0 , 0}; // defines a voltage source

In order to find a minimum common time step, delaying and then executing the update of the equivalent resistances and currents I have to pass information around.

This boils down to associate to a SVAnet variables with the following requirements:

  • they can be set independently of {V, I, R}
  • resolution function for {V, I, R} should not react on them
  • no resolution function for them is needed

Clearly, direct extension of SVAstruct would not fulfill the first two requirements.

Ideas?

  • Global variables are a possibility, but I would like to see a more automatic way to communicate among connected SVAnets.
  • Creating a class or using a substructure on which the resolution works come to my mind but are beyond my programming skills.
bardo
  • 390
  • 1
  • 9
  • Not sure what you are asking for. There are no resolution functions associated with variables; last write wins. Can you edit your post and show an example of what kinds of values you want to see on S and P? – dave_59 Apr 01 '17 at 12:14
  • Thx, background added. – bardo Apr 01 '17 at 15:06
  • I understand how the resolution function works with multiple driven nets, but there can only be one driver of a variable in SystemVerilog. Resolution function does not apply to a variable. A struct variable behaves the same as it would in any other programming language like C/C++. – dave_59 Apr 04 '17 at 17:08

0 Answers0