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I'm looking at the Store instruction caching modes table within the PTX ISA specification (for PTX v2). It provides details regarding four caching modes:

  • .wb: Cache write-back all coherent levels

  • .cg: Cache at global level (cache in L2, not L1)

  • .cs: Cache streaming, likely to be accessed once

  • .wt: Cache write-through (to system memory)

The explanatory text is somewhat confusing for me.

Which modes will result in an immediate change to the L1 cache, the L2 cache and to the global memory, for the line being written to (as opposed to other lines which need to be evicted)? I'll post what I understand from the text as an answer, please correct me if I'm wrong.

Note: Let's ignore local and shared memory for the sake of this question.

talonmies
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einpoklum
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1 Answers1

2

(Edit: On second reading, I have low confidence in this answer.)

When no evictions are necessary, a store instruction results in the following kinds of writes:

Mode L1 L2 Global
wb Yes No No
cg No Yes No
cs Yes No No
wt Yes Yes Yes

when all possible evictions occur, the above changes into the following:

Mode L1 L2 Global
wb Yes Yes Yes
cg No Yes Yes
cs Yes Yes Yes
wt Yes Yes Yes

Caveat: this is based on my understanding of the PTX ISA documentation and nothing else.

einpoklum
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