GCC 6 shift over flow error,

Question

  CC      drivers/iommu/msm_iommu-v1.o
In file included from include/linux/io.h:22:0,
                 from drivers/iommu/msm_iommu-v1.c:18:
drivers/iommu/msm_iommu-v1.c: In function '__program_context':
arch/arm/mach-msm/include/mach/iommu_hw-v1.h:61:31: warning: 
result of '16777215 << 14' requires 39 bits to represent, 
but 'int' only has 32 bits [-Wshift-overflow=]
error, forbidden warning: iommu_hw-v1.h:61

This has been asked before. Android kernel compile error gcc6 linaro 6 The only answer give was to compile with

 # Ensure C builds don't fail on warnings 
 export CFLAGS="-Wno-error" 
 export CXXFLAGS="-Wno-error"

This makes no sense to me, why hide error? We should fix them. Here is what I've found so far.

drivers/iommu/msm_iommu-v1.c: In function '__program_context'

static void __program_context(struct msm_iommu_drvdata *iommu_drvdata,
                  struct msm_iommu_ctx_drvdata *ctx_drvdata,
                  struct msm_iommu_priv *priv, bool is_secure,
                  bool program_m2v)
{
    unsigned int prrr, nmrr;
    phys_addr_t pn;
    void __iomem *base = iommu_drvdata->base;
    unsigned int ctx = ctx_drvdata->num;
    phys_addr_t pgtable = __pa(priv->pt.fl_table);

    __reset_context(base, ctx);

    pn = pgtable >> CB_TTBR0_ADDR_SHIFT;
    SET_TTBCR(base, ctx, 0);
    SET_CB_TTBR0_ADDR(base, ctx, pn);

    /* Enable context fault interrupt */
    SET_CB_SCTLR_CFIE(base, ctx, 1);

    /* Redirect all cacheable requests to L2 slave port. */
    SET_CB_ACTLR_BPRCISH(base, ctx, 1);
    SET_CB_ACTLR_BPRCOSH(base, ctx, 1);
    SET_CB_ACTLR_BPRCNSH(base, ctx, 1);

    /* Turn on TEX Remap */
    SET_CB_SCTLR_TRE(base, ctx, 1);

    /* Enable private ASID namespace */
    SET_CB_SCTLR_ASIDPNE(base, ctx, 1);

    /* Set TEX remap attributes */
    RCP15_PRRR(prrr);
    RCP15_NMRR(nmrr);
    SET_PRRR(base, ctx, prrr);
    SET_NMRR(base, ctx, nmrr);

    /* Configure page tables as inner-cacheable and shareable to reduce
     * the TLB miss penalty.
     */
    if (priv->pt.redirect) {
        SET_CB_TTBR0_S(base, ctx, 1);
        SET_CB_TTBR0_NOS(base, ctx, 1);
        SET_CB_TTBR0_IRGN1(base, ctx, 0); /* WB, WA */
        SET_CB_TTBR0_IRGN0(base, ctx, 1);
        SET_CB_TTBR0_RGN(base, ctx, 1);   /* WB, WA */
    }

    if (!is_secure) {
        if (program_m2v)
            program_all_m2v_tables(iommu_drvdata);

        SET_CBAR_N(base, ctx, 0);

        /* Stage 1 Context with Stage 2 bypass */
        SET_CBAR_TYPE(base, ctx, 1);

        /* Route page faults to the non-secure interrupt */
        SET_CBAR_IRPTNDX(base, ctx, 1);

        /* Set VMID to non-secure HLOS */
        SET_CBAR_VMID(base, ctx, 3);

        /* Bypass is treated as inner-shareable */
        SET_CBAR_BPSHCFG(base, ctx, 2);

        /* Do not downgrade memory attributes */
        SET_CBAR_MEMATTR(base, ctx, 0x0A);

    }

    msm_iommu_assign_ASID(iommu_drvdata, ctx_drvdata, priv);

    /* Enable the MMU */
    SET_CB_SCTLR_M(base, ctx, 1);
    mb();
}

arch/arm/mach-msm/include/mach/iommu_hw-v1.h

#define SET_FIELD(addr, mask, shift, v) \
do { \
    int t = readl_relaxed(addr); \
    writel_relaxed((t & ~((mask) << (shift))) + (((v) & \
            (mask)) << (shift)), addr); \
} while (0)

The issue from what I can tell is the function writel_relaxed from arch/arm/include/asm/io.h

#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
                cpu_to_le32(v),c))

Files

iommu_hw-v1.h

msm_iommu-v1.c

arch/arm/include/asm/io.h

Github Kernel Source

What is difficult to understand here? The warning clearly states that `16777215 << 14` would overflow the 32 bit variable and it is probably not the expected behavior. — Ajay Brahmakshatriya, Mar 19 '17 at 09:16

Ajay Brahmakshatriya · Answer 1 · 2017-03-19T10:15:15.237

0

Solution in simple words - Use a bigger width variable. Use unsigned long long in place of int.

Edit : In case the macro is being called on constants and not variables, cast the constant explicitly to (unsigned long long). I am not sure if C standards have constant suffixes for long long.

edited Mar 19 '17 at 10:15

answered Mar 19 '17 at 09:17

Ajay Brahmakshatriya

8,993
3
26
49

These aren't variables but constants – Antti Haapala -- Слава Україні Mar 19 '17 at 10:10

Antti Haapala -- Слава Україні · Answer 2 · 2017-03-19T10:09:56.613

0

The error comes from the macro expansion of SET_FIELD. 16777215, an int constant, is used as the mask value there:

#define SET_FIELD(addr, mask, shift, v) \
do { \
    int t = readl_relaxed(addr); \
    writel_relaxed((t & ~((mask) << (shift))) + (((v) & \
            (mask)) << (shift)), addr); \
} while (0)

The constant could possibly need to be cast to unsigned int, or perhaps even a wider type if this is about 64-bit ARM. However, it is not clear from just the source and warning where this macro SET_FIELD is being called.

OR, possibly by casting the mask in the macro above to (unsigned int).

edited Mar 19 '17 at 10:09

answered Mar 19 '17 at 09:46

Antti Haapala -- Слава Україні

129,958
22
279
321

So I need to find where 16777215 is declared? – Jcfunk Mar 19 '17 at 09:52
@Jcfunk yes, or at least, which of these macro calls in `__program_context` results in the failure – Antti Haapala -- Слава Україні Mar 19 '17 at 10:03

GCC 6 shift over flow error,

drivers/iommu/msm_iommu-v1.c: In function '__program_context'

arch/arm/mach-msm/include/mach/iommu_hw-v1.h

Files

2 Answers2