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Presuming I have:

x: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
  • y <= x if x is integer

How can I test if my x is a integer number?

Draken
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Elena Tentea
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  • What kind of properties would cause you to define `x` as being an "integer"? As shown, `x` is never an `integer`; it is a `std_logic_vector`. If you're trying to avoid propagating `x` to `y` when some of the bits of `x` are `'U'`,`'X'`,`'Z'`, or `'W'`, then that's what you should ask. Checking for that is possible for simulation, but won't mean anything for synthesis because in real hardware a `std_logic_vector` (and any other physically representable type) always results in an aggregate of `'1'`s and `'0'`s. – QuantumRipple Mar 16 '17 at 17:19
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    If it's an integer, its type should be numeric_std.signed (or unsigned) rather than std_logic_vector. –  Mar 16 '17 at 20:50

1 Answers1

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A std_logic_vector is a composite type, an array type comprised of elements of a discrete enumerated type (the base type std_ulogic which represents 9 values 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H' and '-'). '0' and '1' represent forcing binary bit values, 'L' and 'H' represent weak binary bit values and the rest are metalogical values (except 'Z' which is used to signal high impedance of a driver, see IEEE Std 1076-2008 16.8.2.4 Interpretation of logic values).

IEEE Std 1076-2008 has two packages of use in evaluating std_logic_vector as binary representations of integer values either directly: package numeric_std_unsigned assumes a std_logic_vector value has a natural range binary value convertible to a numeric_std unsigned type (similar to the Synopsys package std_logic_arith_unsigned), or indirectly through type conversion using package numeric_std, either to type unsigned for binary numbers or type signed for twos complement numbers including negative numbers.

For evaluating a type signed or unsigned representing a binary number for the presence of metalogical values or 'Z's package numeric_std uses a function IS_X declared for both signed and unsigned which returns a Boolean true if the parameter actual contains a metalogical value or 'Z'.

When using package numeric_std_unsigned to interpret std_logic_vector values as unsigned the IS_X function used is defined in package std_logic_1164 and operates on a std_logic_vector parameter without type conversion.

The weak values 'L' and 'H' are not mapped to '0' and '1' by assignment. In the -2008 version of package std_logic_1164 a function TO_01 is included that will map 'L' and 'H' to '0' and '1' should you compare y to string literal in a condition or a choice.

Using -2008 packages std_logic_1164 and numeric_std_unsigned an assignment insuring y contains a binary representation in of unsigned integers would use function TO_01:

y <= TO_01(x) when not IS_X(x);

Or with an if statement in a process statement or place appropriate for a sequential statement:

if not IS_X(x) then
    y <= TO_01(x);
end if;

Neither of the used function calls have any bearing on synthesis where metalogical values are not used in proofs (while 'Z' has special meaning).

If you can guarantee x never contains an 'L' or an 'H', function TO_01 can be eliminated.

There's a consequence of only conditionally assigning y in simulation. If x contains a metalogical value or 'Z' the assignment will not take place leaving the last value of y as y. This can have unintended consequence that under some circumstances should be brought to the attention of the user because simulation will not match synthesized behavior. Notification can be done by introducing an overload function for IS_X or otherwise a new function that reports metalogical values or 'Z' are found here.