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Assembly Code:

lw  R1, 0(R2)
add R4, R3, R1
add R3, R1, R4

What are the dependencies?

Fill the pipelining timeline if:
a. There is forwarding
b. There is no forwarding

Instruction 1 and 2 have a dependency for R1. Instruction 2 and 3 have a dependency for R4.

Below are my two attempts for part a and part b respectively:

Attempt at part A

Attempt at part B

Am I filling the pipelining timeline correctly?

PsiX
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John D
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  • please dont use links post the complete question here on stack overflow. and put a little bit more than am I doing this correctly. have a real question. – old_timer Mar 11 '17 at 17:49
  • That is basically the question. Given assembly code, fill the pipelining timeline. The links I posted was an image of my attempt at filling the pipeline. – John D Mar 11 '17 at 17:56
  • links are not useful, either post the images or re-create the information in the question, not links. then add more to the question. I think there is no pipeline delay here because, but think there is one here because, is that correct. is that correct...should I have, is that correct. – old_timer Mar 11 '17 at 20:50
  • The question was posted in completeness. The original prompt gives the assembly code and says to fill the pipelining timeline if there is data forwarding and if there isn't data forwarding. The imgur links I posted were my attempt at filling the pipelining timeline. – John D Mar 11 '17 at 22:53
  • links are frowned upon at stackoverflow, the links can go away independently of the question making the question have no value for folks that come along later looking for help with things, many folks will not open the links to answer your question, so if the information in the links are required then you need to move those images or recreate them on the stackoverflow server. – old_timer Mar 11 '17 at 23:43
  • Images have been uploaded to the stackoverflow server. – John D Mar 11 '17 at 23:59
  • I am just trying to help you from having your ticket get closed for one of multiple reasons... – old_timer Mar 11 '17 at 23:59
  • I understand and appreciate that, but your first few pieces of advice were pretty confusing because my attempt at the problem was via a picture. The attempted solution be much harder to read if not in picture form. That being said, I have reuploaded the images to the stackoverflow server. – John D Mar 12 '17 at 00:03
  • As you can see I have answered thousands of question but only asked a very few, it is possible though as I have seen it hundreds of times to have images mixed in with the text, that was what I was aiming for. From your score I understand you are very new to stackoverflow... – old_timer Mar 12 '17 at 00:14
  • so clearly forwarding is a vocabulary word and from your images you are basically grabbing r1 either after/at execution or after at write back. and certainly r1 is the dependency that affects all three instructions. the read has to complete before you can do the adds... – old_timer Mar 12 '17 at 00:17
  • what does ID stand for? would the add want a stalled state while it waited for the result from lw? is id the right state name for that? – old_timer Mar 12 '17 at 00:18
  • Are you referring to a or b? In a, forwarding is allowed, so the value of new value R1 is available right after MEM stage and is forwarded to the EX stage of the 2nd instruction. In b, forwarding is not allowed, so the second instruction needs to wait for the WB stage for the new value of R1. – John D Mar 12 '17 at 00:20
  • ID is instruction decode. Im confused on that part because I have seen examples where stalls are inserted and other examples where ID is simply repeated until the data dependency is 'fixed'. – John D Mar 12 '17 at 00:21
  • duh, yeah figured that out just as I was turning off the computer. knew it was the decode, but what was the I for then it dawned on me. yeah i would go with what the textbook or professor shows for those states where it is basically waiting for something to complete. – old_timer Mar 12 '17 at 01:37
  • The problem is my professor does it two different ways from the textbook. He's used repeated fetching, repeated decode, and stalls interchangeably and I have no idea when to use which. – John D Mar 12 '17 at 01:39
  • the second instruction requires R1 to have loaded from the first, the third instruction needs both R1 and R4. and it is clear from your picture that forwarding meas you can "forward" the value for the register to the next stage in the pipe without that stage having to wait to actually read it from the register file (after write back). And not forwarding means you have to wait for the dependencies to be written to the register file before you cant get them (from the register file). – old_timer Mar 12 '17 at 01:39
  • well just be consistent then. in both the add cases either repeat IDs or use stalls but have one do one and the other do the other...And perhaps just go ask the professor when you can what he/she prefers... – old_timer Mar 12 '17 at 01:40
  • sadly it is a bit too late to ask the professor. Functionally, is a stall different from a repeated ID? – John D Mar 12 '17 at 01:41
  • It really depends on the implementation, since this is no doubt textbook/paper stuff and not a logic implementation (or not yet) then it depends on how you design the logic as to what the states are and what they depend on you could have a stall state and the exit from that state to the next is the resolution of the dependencies, or could have a decode state and the exit from that state includes resolving all the dependencies. From the time these first mips textbooks were written actually implementation and number of states and names and functionality vary with each design/generation. – old_timer Mar 12 '17 at 01:44
  • the terms are valid terms to use, but you hear of 15 stage pipeline designs or 3 stage, etc..and I wouldnt be surprised if there are patents on one/some of those or at least attempts at patents. So you really have to communicate for this class using the terms for this class, the next class may be different terms or states. If the professor has gone both ways with it then pick one and argue that he/she went both ways and you picked one (if there is an issue). – old_timer Mar 12 '17 at 01:46
  • saying "some old guy on stackoverflow said" is not going to get you very far BTW... – old_timer Mar 12 '17 at 01:47
  • It may just be nomenclature, but usually, if a stage stalls, the "box" is blank to indicate the stall. The processor doesn't stall in the `ID` stage by repeatedly sending it through the `ID` circuitry (e.g.). If it did, a subsequent inst would have to "stall" waiting for the `ID` circuitry to become available. `IF` and `ID` never have to wait for anything. Consider how wasteful it would be if `IF` refetched from memory. Also, `IF` runs one ahead and is "blind" to what the other stages do. As is `ID`. It's only _after_ `ID` that a need for stall can be deduced [to hold up `EX`] – Craig Estey Mar 12 '17 at 04:01
  • @CraigEstey This is why I am so confused. I see some examples where a stall is `-`, some where it is a NOP, and some where ID and IF are repeated during the stalled boxes. – John D Mar 12 '17 at 04:39

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