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I have figured out that for two unsigned integers, I can just do this:

sll $a0, $a0, 31                          #a0 is integer 1 to be added

sll $a1, $a1, 31 #a1 is integer 2

add $t0, $a0, $a1 #result in $t0

addi $t1, $0, 2

beq $v0, $t0, $t1

What this does is it shifts the 32nd bit of both integers to the first bit spot and it adds them. If both of these numbers are 1, then the answer in $t1 will be 2 (01+01=10). Therefore, an overflow has occurred.

However for signed integers, the leading one signifies negative integers. I've ruled out the possibility for an overflow is both integers are off opposite sign, but suppose they are the same sign. Then 010 + 011 (two positive integers) will give me 101, but because this is signed. This becomes a negative integer. Would I just check if the number has changed signs? And for two negative integers, I can just check as if it were unsigned?

Michael
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mamajava
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    Even your unsigned doesn't work too well. Your `beq` is invalid syntax and uses `$v0` without being inited. You want to _right_ shift, so you want `srl` instead of `sll`. And the test fails. If both numbers are -1 (i.e. `0xFFFFFFFF`), when you add them you get -2 (i.e. `0xFFFFFFFE`). This does _not_ cause an overflow. But, I believe your test would think it would. – Craig Estey Mar 08 '17 at 19:01

1 Answers1

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So you are talking about signed overflow? If the carry in does not match the carry out then it is a signed overflow.

abi or
000 00
001 01 signed overflow
010 01
011 10
100 01
101 10
110 10 signed overflow
111 11

a and b are the operands, i is the carry in, o is carry out and r is result.

notice anything about the relationship between a, b, and r? You can determine signed overflow by simply looking at the msbits of the two operands and the result.

This has absolutely nothing to do with mips, it is basic twos complement addition (and subtraction). To apply it to an instruction set you need to isolate the msbits of the operands and if they match the result. Can use a test/and can use, shifting 31 bits assuming it pads with something known (like zero and not sign extends, or maybe sign extension helps). add with zero check the z flag. mips doesnt use flags so and or shift to isolate then compare if equal or not is a good generic solution. can test carry in vs carry out as well (and both operands with 0x7FFFFFFF then add, then shift right 31, and or isolate the carry in and the two operand msbits, then add those three items and see if the carry out is the same or different, takes a lot more instructions).

old_timer
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