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I am a Verilog user trying to make sense of VHDL code of AXI4 Master bus functional model (BFM)

AXI4 Master Bus functional model VHDL code

I have a few questions from the above code

What would block diagram of the code look like (how are components connected with each other)

Lastly, what is the use of FIFO? I mean to connect AXI master to AXI slave, can't one connect the appropriate signals directly as shown in the picture? What purpose does FIFO serve here and what if it is removed?

AXI Master-Slave connection

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    This is not really a VHDL language question. You might get a better response over at http://electronics.stackexchange.com – scary_jeff Feb 23 '17 at 10:36
  • The code you are linking to does not represent the image you show. The code seems to connect user logic to an AXI4 master port. The fifo is there because the user logic uses a fifo read-write interface, while the AXI4 bus uses a clock. I think the code was designed using a design automation tool like mentor HDL designer. It is very unreadable this way. It seems to use an asynchronous state machine process. – JHBonarius Feb 23 '17 at 13:47

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