iverilog syntax for include?

Question

I'm trying to include a Verilog file (alu.v) in my main file (cpu.v). Both files are in the same directory.

'include "alu.v"

 module cpu();
 ...
 ...
 endmodule

When I try to compile it, I get the following error.

cpu.v:1 syntax error
I give up

I don't see how the include statement is wrong. I'm sure my syntax is correct like shown here.

Answer 1

Don't be so sure! Proof you mess with something, it does not work.

The preprocessor directives in Verilog begin with a back-tick (`) not an apostrophe (').

Try:

`include "alu.v"

Instead of:

'include "alu.v"